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什么是状态机：状态机通过不同的状态迁移来完成特定的逻辑操作

状态机的分类：Moore型状态机和Mealy型状态机

Moore型：状态机的变化只与当前的状态有关
Mealy型：状态机的变化不仅与当前的状态有关，还与输入有关

如何创建状态机：状态机的创建可以分为一段式，两段式和三段式

一段式：主要是讲所有的状态变化以及导致的输出变化都写在了一个always快中。
两段式：将一些复位信号，clk信号单独写在一个always快中，其他的状态变化，输出值得变化写在一个always快中。
三段式：将一些复位信号，clk信号单独写在一个always快中，其他的状态迁移变化写在一个always快中，对应状态的输出值得变化写在一个always快中。

举个例子：从循环输入的字母中做连续检测，当连续检测到“hello”时，将led灯进行状态的翻转，继续进行下一次的检测。

一段式的编写方式:

module  hello(
input clk,//系统时钟信号  50mHz
input rst_n,//系统复位信号，低电平有效
input [7:0] data,//连续输入的字母
output reg led//led灯
);

//设置需要改变的状态
parameter    checkh  = 5'b0000_1,
             checke  = 5'b0001_0,
             checkla = 5'b0010_0,
             checklb = 5'b0100_0,
             checko = 5'b1000_0;

reg [4:0]state;

always @(posedge clk or negedge rst_n)
    if(!rst_n)
        begin
            led <= 1'b0;
            state <= checkh;
        end
    else
        begin
            case (state)
                checkh:
                    if(data == "h") state <= checke;
                    else  state <= checkh;
                checke:
                    if(data == "e") state <= checkla;
                    else  state <= checkh;
                checkla:
                    if(data == "l") state <= checklb;
                    else  state <= checkh;
                checklb:
                    if(data == "l") state <= checko;
                    else  state <= checkh;
                checko:
                    if(data == "o")
                        begin
                        led <= ~led;
                        state <= checkh;
                        end
                    else  state <= checkh;
                default:state <= checkh;
            endcase
        end

endmodule12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849

两段式的编写方式:

module  hello(
input clk,
input rst_n,
input [7:0] data,
output reg led
);

parameter checkh  = 5'b0000_1,
             checke  = 5'b0001_0,
             checkla = 5'b0010_0,
             checklb = 5'b0100_0,
             checko = 5'b1000_0;

reg [4:0] cstate;
reg [4:0] nstate;

always @(posedge clk or negedge rst_n)
if(!rst_n)
        begin
            cstate <= checkh;
        end
else
            cstate <= nstate;

always @(cstate or data)
            case (cstate)
                checkh:
                    if(data == "h") nstate <= checke;
                    else  nstate <= checkh;
                checke:
                    if(data == "e") nstate <= checkla;
                    else  nstate <= checkh;
                checkla:
                    if(data == "l") nstate <= checklb;
                    else  nstate <= checkh;
                checklb:
                    if(data == "l") nstate <= checko;
                    else  nstate <= checkh;
                checko:
                    if(data == "o")
                        begin
                        led <= ~led;
                        nstate <= checkh;
                        end
                    else  nstate <= checkh;
                default:nstate <= checkh;
            endcase

endmodule123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051

三段式的编写方式:

module  hello(
input clk,
input rst_n,
input [7:0] data,
output reg led
);

parameter checkh  = 5'b0000_1,
             checke  = 5'b0001_0,
             checkla = 5'b0010_0,
             checklb = 5'b0100_0,
             checko = 5'b1000_0;

reg [4:0] cstate;
reg [4:0] nstate;

    //复位信号，clk的处理（主要是对初始状态进行赋值操作）
always @(posedge clk or negedge rst_n)
if(!rst_n)
        begin
            cstate <= checkh;
        end
else
            cstate <= nstate;

    //状态迁移的处理
always @(cstate or data)
            case (cstate)
                checkh:
                    if(data == "h") nstate <= checke;
                    else  nstate <= checkh;
                checke:
                    if(data == "e") nstate <= checkla;
                    else  nstate <= checkh;
                checkla:
                    if(data == "l") nstate <= checklb;
                    else  nstate <= checkh;
                checklb:
                    if(data == "l") nstate <= checko;
                    else  nstate <= checkh;
                checko:
                    if(data == "o")
                        begin
                        nstate <= checkh;
                        end
                    else  nstate <= checkh;
                default:nstate <= checkh;
            endcase

    //输出数据的处理
always @(posedge clk or negedge rst_n)
if(!rst_n)
        begin
            led <= 1'b1;
        end
else
        case (cstate)
                checko:
                    if(data == "o")
                    led <= ~led;
                default;
            endcase

endmodule
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版权声明：本文为CSDN博主「ruanyz_china」的原创文章，遵循CC 4.0 by-sa版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/ruanyz_nobody/article/details/49892037