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#include <msp430.h> 1|?K\B
static char String1[] = { "Hello World\r\n" }; w#^U45y1v
IF@HzT;Q
int main(void) {$M;H+Foh
{ -K[782Q
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog XW L^
//....................... Q!M)xNl/
P5SEL |= BIT4+BIT5; // Select XT1 ^I] {7$6^
lr2 rQo >
UCSCTL6 &= ~(XT1OFF); // XT1 On r
Db> &s3
UCSCTL6 |= XCAP_3; // Internal load cap Z7jX9e"L
UCSCTL3 = 0; // FLL Reference Clock = XT1 A7P`lJgv
A.Bk/N1G
// Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle &gc `<kLu
do T[Pa/j{
{ nB5Am^bP
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); <1&Ke
// Clear XT2,XT1,DCO fault flags yW.COWL=)
SFRIFG1 &= ~OFIFG; // Clear fault flags a)2yE,":
}while (SFRIFG1&OFIFG); // Test oscillator fault flag P .sgRsL
50a\e
UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength m h;X~.98
>m _v5K
UCSCTL4 |= SELA_0 + SELS_4 + SELM_4; // ACLK = LFTX1 y7<&vIEC
// SMCLK = default DCO ^^(<c,NX#M
// MCLK = default DCO 0p fnV%
//................ fn9#>~vrD
6(sIYZ2yq
P4SEL = BIT4+BIT5; // P4.4,5 = UART1 TXD/RXD Poa ?Ej
// configure USCI_A1 UART Qrz4 }0
UCA1CTL1 = UCSSEL_1; // ACLK |xr32g s
UCA1BR0 = 0x03; // 32768Hz 9600 32k/9600=3.41 %d: A`7x
UCA1BR1 = 0x0; /f1'm@8;
UCA1MCTL = UCBRS_3+UCBRF_0; // Modulation UCBRSx = 3 v\ZBv zd
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine** F?Or;p5`Y
// configure DMA0 M+s j}
DMACTL0 = DMA0TSEL_1; // 0-CCR2IFG 1h"_[`L'
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) String1); # nfI%
// Source block address v9}[$HWx
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA1TXBUF); a %hGZCI
// Destination single address ]2+g&ox4'
DMA0SZ = sizeof String1-1; // Block size ;Mj002.\G
DMA0CTL = DMADT_4 + DMASRCINCR_3 + DMASBDB + DMAEN;// Rpt, inc src, enable f|xLKcOP
Z{{ t^+XG
TA0CCR0 = 8192; // Char freq = TACLK/CCR0 Xy#V Q{!
TA0CCR2 = 1; // For DMA0 trigger u9![6$R
TA0CTL = TASSEL_1 + MC_1; // ACLK, up-mode >uHS[ _`nM
lv:U%+A
__bis_SR_register(LPM3_bits); // Enter LPM3 rbk< z\pc
} 0^]t"z5f0
