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有用过mst703驱动群创10.2寸液晶屏AT102TN03的吗？ [复制链接]

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关键词： 驱动程序mstar液晶
最近用mst703驱动群创10.2寸液晶屏AT102TN03，程序用的是mstar提供的公版maria软件。目前已经可以通过按键开关机了，但就是一直白屏。因程序里没有提供10.2寸屏的头文件，是我自己拿别的头文件改的，因此判断是屏参数配置错误。做过的帮忙看下哪里出了问题（估计是在上电时序和一堆寄存器参数那块），要是能发我一份就最好了。 ^Q\O8f[u  
复制代码
  1. #include "ms_reg.h"
  3. #ifndef _PNL_AT102TN03_H_
  4. #define _PNL_AT102TN03_H_
  6. #include "devvd.h"
  8. #define        PanelName        "PnlAT102TN03" //
  9. #define WidePanel                0      //
  11. #define PanelDither                    8      //
  13. #define PANEL_TTL                    1
  14. #define PANEL_DIGITAL_TCON  0
  15. #define PANEL_ANALOG_TCON        0
  17. #define PANEL_LVDS_TI_MODE    0
  18. #define PANEL_SWAP_LVDS_POL   1
  19. #define PANEL_SWAP_LVDS_CH    0
  21. #define PanelSwapRB                        (0xFF)
  22. #define PanelSwap8BitML                0//0x0F
  23. #define PanelSwap6BitML                0
  25. #define PanelDClkDelay                0
  26. #define PanelInvDE                    0
  27. #define PanelInvDClk                (0x0F)
  28. #define PanelInvHSync                0
  29. #define PanelInvVSync                0
  31. // driving current setting 0==>4mA, 1==>6mA, 2==>8mA ,3==>12mA
  32. #define PanelDCLKCurrent        0 // Dclk current
  33. #define PanelDECurrent                0 // DE signal current
  34. #define PANELHSCURRENT                   0 // HSYNC current
  35. #define PANELVSCURRENT                   0 // VSYNC current
  36. #define PANELBMCURRENT                   0 // B data High-Nibble current
  37. #define PANELBLCURRENT                   0 // B data Low-Nibble current
  38. #define PANELGMCURRENT                   0 // G data High-Nibble current
  39. #define PANELGLCURRENT                   0 // G data Low-Nibble current
  40. #define PANELRMCURRENT                   0 // R data High-Nibble current
  41. #define PANELRLCURRENT                   0 // R data Low-Nibble current
  42. #define PANELADCLKCURRENT        0 // Analog Panel DCLK current
  44. #if SYSTEM_BOOT_UP_QUICKLY_ENABLE
  45. #define PanelOnTiming1                20//20 // time between panel & data while turn on power
  46. #define PanelOnTiming2                20//20 // time between data & back light while turn on power
  47. #define PanelOffTiming1                2 // time between back light & data while turn off power
  48. #define PanelOffTiming2                2 // time between data & panel while turn off power
  49. #else
  50. #define PanelOnTiming1                100 //100 time between panel & data while turn on power
  51. #define PanelOnTiming2                100 //100 time between data & back light while turn on power
  52. #define PanelOffTiming1                20 //20 time between back light & data while turn off power
  53. #define PanelOffTiming2                20 //20 time between data & panel while turn off power
  54. #endif
  56. #define PanelHSyncWidth                40
  57. #define PanelHSyncBackPorch        44
  59. #define PanelVSyncWidth                 4
  60. #define PanelVSyncBackPorch         34
  62. #define PANEL_DE_VSTART        0
  63. #define PanelHStart                (PanelHSyncWidth+PanelHSyncBackPorch) //88
  64. #define PanelVStart                (PanelVSyncWidth+PanelVSyncBackPorch) //38
  65. #define PanelWidth                800
  66. #define PanelHeight                480
  67. #define PanelHTotal                1080
  68. #define PanelVTotal                525
  70. #define PanelVdeEnd     PanelHeight
  71. #define PanelVSiEnd     PanelHeight
  73. #define PanelMinHTotal                1080
  74. #define PanelDCLK                        (((DWORD)PanelHTotal*PanelVTotal*60)/1000000)
  76. ///////////////////////////////////////////////////////
  77. // TCON setting
  78. ///////////////////////////////////////////////////////
  80. // PTC Mode setting
  81. #define SET_PTC_MODE1                0x8C        // PTC_MODE1(0xD0)
  82. #define SET_PTC_MODE2       0x46
  83. #define SET_PTC_MODE2_NOR        0x36        // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
  84. #define SET_PTC_MODE2_INV        0x31        // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
  85. #define SET_PTC_MODE3                0x82        // PTC_MODE3(0xD2)
  87. // PTC Timming Setting
  88. #define SET_FRP_TRAN                0x02        // GPO_FRP_TRAN(0xDC)
  89. #define SET_STH_START                0x35        // GPO_STH_START(0xDD) ORG:0x2C
  90. #define SET_STH_WIDTH                0x01        // GPO_STH_WIDTH(0xDE)
  91. #define SET_OEH_START                0x00        // GPO_OEH_START(0xDF)
  92. #define SET_OEH_WIDTH                0x2C        // GPO_OEH_WIDTH(0xE0)
  93. #define SET_OEV_START                0x6C        // GPO_OEV_START(0xE1)
  94. #define SET_OEV_WIDTH                0x29        // GPO_OEV_WIDTH(0xE2)
  95. #define SET_CKV_START                0x2A        // GPO_CKV_START(0xE3)
  96. #define SET_CKV_START2                0x00        // GPO_CKV_START2(0xE4)
  97. #define SET_CKV_WIDTH                0x1C        // GPO_CKV_WIDTH(0xE5)
  98. #define SET_STV_LINE_TH                0x44        // GPO_STV_LINE_TH(0xE6)
  99. #define SET_STV_START                0x6F        // GPO_STV_START(0xE7)
  100. #define SET_STV_WIDTH                0x00        // GPO_STV_WIDTH(0xE8)
  101. #define SET_OEV2_START                0x00        // GPO_OEV2_START(0xE9)
  102. #define SET_OEV3_START                0x00        // GPO_OEV3_START(0xEA)
  103. #define SET_H_ST_DLY_L                0x00        // H_ST_DLY_L(0xEB)
  104. #define SET_H_ST_DLY_H                0x00        // H_ST_DLY_H(0xEC)
  105. #define SET_CLK_DLY_SYNC_OUT        0x00        // CLK_DLY_SYNC_OUT(0xED)
  106. #define SET_CKV_END2                0x00        // GPO_CKV_END2(0xEE)
  107. #define SET_Q1H                         0x00        // Q1H_SETTING(0xEF)
  110. #define SET_OEV2_WIDTH                0x54        // GPO_OEV2_WIDTH(0xCD)
  111. #define SET_OEV3_WIDTH                0x54        // GPO_OEV3_WIDTH(0xCE)
  112. #define SET_OEV_DELTA                0x54        // GPO_OEV_DELTA(0xCF)
  114. // VCOM setting
  115. #define SET_BVOM_DC                    0xA0        //DEF_VCOM_DC        // BVOM_DC(0x43)
  116. #define SET_BVOM_OUT                0xA0        //DEF_VCOM_AC        // BVOM_OUT(0x44)
  118. // DAC setting
  119. #define SET_VDAC_ADJ1                0x00        // VADC_ADJ1(0xAA)
  120. #define SET_VDAC_ADJ2                0x00        // VDAC_ADJ2(0xAB)
  122. // Video decoder
  123. #define _656_PLL_VALUE                0x83        //BK2_9D_DPL_NSPL_HIGH
  124. #define COCTRL1_VALUE                 0x20
  127. #define SVD_EN_VALUE0                0x40        //BK2_1A_SVD_EN
  129. #define BK1_7B_TERM_SEL_VALUE                0xE4
  130. #define BK1_7C_CROING_VALUE                        0x64
  132. #define PANEL_SYNC_MODE_1   0
  134. #define ENABLE_VSYNC_CTL_AUTO_H_TOTAL   0// 1
  135. #define ENABLE_CHECK_AUTO_H_TOTAL                0// 1
  137. #define ENABLE_OVER_SCAN                    1
  138. #define VD_OVER_SCAN_H                 00 // 1.0%
  139. #define VD_OVER_SCAN_V                 24 // 1.0%
  141. #define BK0_03_SYNC_Sample_Edge    0x98//0x98
  143. #define PANEL_LOCK_Y_LINE                        2
  145. #ifdef _VDCaptureSetting_
  146. code _CaptureVideoWinType tMsVDCapture[SIG_NUMS] = // For internal VD
  147. {
  148.     {0x78, 0x14, 1340,     480}, // NSTC
  149.     {0x7D, 0x0E, 1340,     576}, // PAL
  150.     {0x85, 0x1A, 1340,     576}, // SECAM
  151.     {0x85, 0x1A, 1340,     480}, // NTSC-443
  152.     {0x85, 0x1A, 1340,     480}, // PAL-60
  153.     {0x85, 0x1A, 1340,     480}, // PAL-M
  154.     {0x85, 0x1A, 1340,     576}, // PAL-Nc
  155. };
  157. code _CaptureSvideoWinStartType tSvideoCaptureStart[SIG_NUMS] = // For internal VD
  158. {
  159.     {0x4d, 0x02}, // NSTC
  160.     {0x5f, 0x0f}, // PAL
  161.     {0x5f, 0x0f}, // SECAM
  162.     {0x4d, 0x02}, // NTSC-443
  163.     {0x5f, 0x0f}, // PAL-60
  164.     {0x5f, 0x0f}, // PAL-M
  165.     {0x5f, 0x0f}, // PAL-Nc
  166. };
  167. #endif
  169. #define FreeRunHTotal                0x4A7
  170. #define PalHTotal                        0x4A7
  171. #define NtscHTotal                        0x593
  173. #ifdef EnableUseModeTbl
  174. RegUnitType code tENDModeTbl[]=
  175. {
  176. {_END_OF_TBL_,0},
  177. };
  179. RegUnitType code tNtscModeTbl[]=
  180. {//Reg     Vale
  181. {_END_OF_TBL_, 0x00},
  182. };
  184. RegUnitType code tPalModeTbl[]=
  185. {//Reg     Vale
  186. {_END_OF_TBL_, 0x00},
  187. };
  189. #if CCIR656_ENABLE
  190. RegUnitType code tCCIR656_PalModeTbl[]=
  191. {//Reg     Vale
  192. {BK0_05_SPRVST_L, 0x1e},
  193. {BK0_06_SPRVST_H, 0x00},
  194. {BK0_07_SPRHST_L, 0x45},
  195. {BK0_08_SPRHST_H, 0x01},
  196. {BK0_0B_SPRHDC_L, 0xc4},
  197. {BK0_27_OPL_SET2, 0x36},
  198. {BK0_30_SRH_L, 0x00},
  199. {BK0_31_SRH_M, 0x36},
  200. {BK0_32_SRH_H, 0xcb},
  201. {BK0_34_SRV_M, 0x78},
  202. {_END_OF_TBL_, 0x00},
  203. };
  205. RegUnitType code tCCIR656_NtscModeTbl[]=
  206. {//Reg     Vale
  207. {BK0_05_SPRVST_L, 0x1e},
  208. {BK0_06_SPRVST_H, 0x00},
  209. {BK0_07_SPRHST_L, 0x45},
  210. {BK0_08_SPRHST_H, 0x01},
  211. {BK0_0B_SPRHDC_L, 0xb1},
  212. {BK0_30_SRH_L, 0x00},
  213. {BK0_31_SRH_M, 0x20},
  214. {BK0_32_SRH_H, 0xc9},
  215. {_END_OF_TBL_, 0x00},
  216. };
  217. #endif
  219. #if VGA_ENABLE
  221. RegUnitType code t640_480_60Hz_VGA_ModeTbl[]=
  222. {//Reg     Vale
  223. {BK0_00_REGBK,REG_BANK_SCALER},
  224. {BK0_0D_LYL,0x08},
  225. {_END_OF_TBL_, 0x00},
  226. };
  228. RegUnitType code t640_480_72Hz_VGA_ModeTbl[]=
  229. {//Reg     Vale
  230. {BK0_00_REGBK,REG_BANK_SCALER},
  231. {BK0_0D_LYL,0x08},
  232. {_END_OF_TBL_, 0x00},
  233. };
  235. RegUnitType code t640_480_75Hz_VGA_ModeTbl[]=
  236. {//Reg     Vale
  237. {BK0_00_REGBK,REG_BANK_SCALER},
  238. {BK0_0D_LYL,0x08},
  239. {_END_OF_TBL_, 0x00},
  240. };
  242. RegUnitType code t800_600_56Hz_VGA_ModeTbl[]=
  243. {//Reg     Vale
  244. {BK0_00_REGBK,REG_BANK_SCALER},
  245. {BK0_0D_LYL,0x0B},
  246. {_END_OF_TBL_, 0x00},
  247. };
  249. RegUnitType code t800_600_60Hz_VGA_ModeTbl[]=
  250. {//Reg     Vale
  251. {BK0_00_REGBK,REG_BANK_SCALER},
  252. {BK0_0D_LYL,0x0B},
  253. {_END_OF_TBL_, 0x00},
  254. };
  256. RegUnitType code t800_600_72Hz_VGA_ModeTbl[]=
  257. {//Reg     Vale
  258. {BK0_00_REGBK,REG_BANK_SCALER},
  259. {BK0_0D_LYL,0x0B},
  260. {_END_OF_TBL_, 0x00},
  261. };
  263. RegUnitType code t800_600_75Hz_VGA_ModeTbl[]=
  264. {//Reg     Vale
  265. {BK0_00_REGBK,REG_BANK_SCALER},
  266. {BK0_0D_LYL,0x0B},
  267. {_END_OF_TBL_, 0x00},
  268. };
  270. RegUnitType code t1024_768_60Hz_VGA_ModeTbl[]=
  271. {//Reg     Vale
  272. {BK0_00_REGBK,REG_BANK_SCALER},
  273. {BK0_0D_LYL,0x0E},
  274. {_END_OF_TBL_, 0x00},
  275. };
  277. RegUnitType code t1024_768_70Hz_VGA_ModeTbl[]=
  278. {//Reg     Vale
  279. {BK0_00_REGBK,REG_BANK_SCALER},
  280. {BK0_0D_LYL,0x0E},
  281. {_END_OF_TBL_, 0x00},
  282. };
  284. RegUnitType code t1024_768_75Hz_VGA_ModeTbl[]=
  285. {//Reg     Vale
  286. {BK0_00_REGBK,REG_BANK_SCALER},
  287. {BK0_0D_LYL,0x0E},
  288. {BK0_00_REGBK,REG_BANK_SCALER},
  289. {_END_OF_TBL_, 0x00},
  290. };
  292. #endif
  294. #if 0//YPBPR_ENABLE
  295. RegUnitType code t576i_ModeTbl[]=
  296. {//Reg     Vale
  297. {BK0_00_REGBK,REG_BANK_SCALER},
  298. {BK0_0D_LYL,0x05},
  299. {BK0_00_REGBK,REG_BANK_SCALER},
  300. {_END_OF_TBL_, 0x00},
  301. };
  303. RegUnitType code t576p_ModeTbl[]=
  304. {//Reg     Vale
  305. {BK0_00_REGBK,REG_BANK_SCALER},
  306. {BK0_0D_LYL,0x0a},
  307. {BK0_00_REGBK,REG_BANK_SCALER},
  308. {_END_OF_TBL_, 0x00},
  309. };
  311. RegUnitType code t480i_ModeTbl[]=
  312. {//Reg     Vale
  313. {BK0_00_REGBK,REG_BANK_SCALER},
  314. {BK0_0D_LYL,0x04},
  315. {BK0_00_REGBK,REG_BANK_SCALER},
  316. {_END_OF_TBL_, 0x00},
  317. };
  319. RegUnitType code t480p_ModeTbl[]=
  320. {//Reg     Vale
  321. {BK0_00_REGBK,REG_BANK_SCALER},
  322. {BK0_0D_LYL,0x08},
  323. {BK0_00_REGBK,REG_BANK_SCALER},
  324. {_END_OF_TBL_, 0x00},
  325. };
  327. RegUnitType code t720p_50Hz_ModeTbl[]=
  328. {//Reg     Vale
  329. {BK0_00_REGBK,REG_BANK_SCALER},
  330. {BK0_0D_LYL,0x0c},
  331. {BK0_00_REGBK,REG_BANK_SCALER},
  332. {_END_OF_TBL_, 0x00},
  333. };
  335. RegUnitType code t720p_60Hz_ModeTbl[]=
  336. {//Reg     Vale
  337. {BK0_00_REGBK,REG_BANK_SCALER},
  338. {BK0_0D_LYL,0x0b},
  339. {BK0_00_REGBK,REG_BANK_SCALER},
  340. {_END_OF_TBL_, 0x00},
  341. };
  343. RegUnitType code t1080i_50Hz_ModeTbl[]=
  344. {//Reg     Vale
  345. {BK0_00_REGBK,REG_BANK_SCALER},
  346. {BK0_0D_LYL,0x06},
  347. {BK0_00_REGBK,REG_BANK_SCALER},
  348. {_END_OF_TBL_, 0x00},
  349. };
  351. RegUnitType code t1080i_60Hz_ModeTbl[]=
  352. {//Reg     Vale
  353. {BK0_00_REGBK,REG_BANK_SCALER},
  354. {BK0_0D_LYL,0x07},
  355. {BK0_00_REGBK,REG_BANK_SCALER},
  356. {_END_OF_TBL_, 0x00},
  357. };
  359. RegUnitType code t1080p_50Hz_ModeTbl[]=
  360. {//Reg     Vale
  361. {BK0_00_REGBK,REG_BANK_SCALER},
  362. {BK0_0D_LYL,0x06},
  363. {BK0_00_REGBK,REG_BANK_SCALER},
  364. {_END_OF_TBL_, 0x00},
  365. };
  367. RegUnitType code t1080p_60Hz_ModeTbl[]=
  368. {//Reg     Vale
  369. {BK0_00_REGBK,REG_BANK_SCALER},
  370. {BK0_0D_LYL,0x07},
  371. {BK0_00_REGBK,REG_BANK_SCALER},
  372. {_END_OF_TBL_, 0x00},
  373. };
  375. #endif
  377. RegUnitType code tTVSnowModeTbl[]=
  378. {//Reg     Vale
  379. /*
  380. {BK0_00_REGBK,REG_BANK_SCALER},
  381. {BK0_33_SRV_L,0x88},
  382. {BK0_34_SRV_M,0xA1},
  383. {BK0_35_SRV_H,0x88},
  384. {BK0_40_VFDEST_L,0x10},
  385. {BK0_41_VFDEST_H,0x00},
  386. {BK0_44_VFDEEND_L,0xFE},
  387. {BK0_45_VFDEEND_H,0x01},
  388. {BK0_4A_SIVEND_L,0xFE},
  389. {BK0_4B_SIVEND_H,0x01},
  390. {BK0_57_OSCTRL1,0xD6}, */
  391. {_END_OF_TBL_, 0x00},
  392. };
  394. RegUnitType code tFreeRunModeTbl[]=
  395. {//Reg     Vale
  396. /*
  397. {BK0_00_REGBK,REG_BANK_SCALER},
  398. {BK0_27_OPL_SET2, 0x23},
  399. {BK0_40_VFDEST_L,0x00},
  400. {BK0_41_VFDEST_H,0x00},
  401. {BK0_44_VFDEEND_L,0xE9},
  402. {BK0_50_VSST_L, 0xF2},  // vsync start position
  403. {BK0_51_VSST_H, 0x0A},
  404. */
  405. {_END_OF_TBL_, 0x00},
  406. };
  408. #endif
  410. //*******************************************************************
  411. //Ace setting
  412. #define CbGain        0x80
  413. #define CrGain        0x80
  415. #define RedGain                0x80//127
  416. #define GreenGain        0x80//130
  417. #define BlueGain               0x80//126
  419. #define INIT_VIDEO_CONTRAST_X0    80
  420. #define INIT_VIDEO_CONTRAST_X1    100
  421. #define INIT_VIDEO_CONTRAST_X2    140
  422. #define INIT_VIDEO_CONTRAST_X3    150
  423. #define INIT_VIDEO_CONTRAST_X4    160
  425. #define INIT_VIDEO_BRIGHTNESS_X0    0x50
  426. #define INIT_VIDEO_BRIGHTNESS_X1    0x70
  427. #define INIT_VIDEO_BRIGHTNESS_X2    0x80
  428. #define INIT_VIDEO_BRIGHTNESS_X3    0x90
  429. #define INIT_VIDEO_BRIGHTNESS_X4    0xc0
  431. #define INIT_VIDEO_SATURATION_X0    0
  432. #define INIT_VIDEO_SATURATION_X1    60
  433. #define INIT_VIDEO_SATURATION_X2    120
  434. #define INIT_VIDEO_SATURATION_X3    150
  435. #define INIT_VIDEO_SATURATION_X4    200
  437. #define INIT_SV_CONTRAST_X0    80
  438. #define INIT_SV_CONTRAST_X1    100
  439. #define INIT_SV_CONTRAST_X2    128
  440. #define INIT_SV_CONTRAST_X3    150
  441. #define INIT_SV_CONTRAST_X4    180
  443. #define INIT_SV_BRIGHTNESS_X0    0x50
  444. #define INIT_SV_BRIGHTNESS_X1    0x70
  445. #define INIT_SV_BRIGHTNESS_X2    0x80
  446. #define INIT_SV_BRIGHTNESS_X3    0x90
  447. #define INIT_SV_BRIGHTNESS_X4    0xc0
  449. #define INIT_SV_SATURATION_X0    0
  450. #define INIT_SV_SATURATION_X1    80
  451. #define INIT_SV_SATURATION_X2    168
  452. #define INIT_SV_SATURATION_X3    20
  453. #define INIT_SV_SATURATION_X4    255
  455. #define INIT_VGA_CONTRAST_X0    80
  456. #define INIT_VGA_CONTRAST_X1    100
  457. #define INIT_VGA_CONTRAST_X2    128
  458. #define INIT_VGA_CONTRAST_X3    150
  459. #define INIT_VGA_CONTRAST_X4    180
  461. #define INIT_VGA_BRIGHTNESS_X0    0x50
  462. #define INIT_VGA_BRIGHTNESS_X1    0x70
  463. #define INIT_VGA_BRIGHTNESS_X2    0x80
  464. #define INIT_VGA_BRIGHTNESS_X3    0x90
  465. #define INIT_VGA_BRIGHTNESS_X4    0xc0
  467. #define INIT_YPBPR_CONTRAST_X0    80
  468. #define INIT_YPBPR_CONTRAST_X1    100
  469. #define INIT_YPBPR_CONTRAST_X2    128
  470. #define INIT_YPBPR_CONTRAST_X3    150
  471. #define INIT_YPBPR_CONTRAST_X4    180
  473. #define INIT_YPBPR_BRIGHTNESS_X0    0x40
  474. #define INIT_YPBPR_BRIGHTNESS_X1    0x60
  475. #define INIT_YPBPR_BRIGHTNESS_X2    0x80
  476. #define INIT_YPBPR_BRIGHTNESS_X3    0xa0
  477. #define INIT_YPBPR_BRIGHTNESS_X4    0xc0
  479. #define INIT_YPBPR_SATURATION_X0    0
  480. #define INIT_YPBPR_SATURATION_X1    60
  481. #define INIT_YPBPR_SATURATION_X2    128
  482. #define INIT_YPBPR_SATURATION_X3    150
  483. #define INIT_YPBPR_SATURATION_X4    200
  485. #define INIT_MSVD_COMB_YGAIN        0x85     //BK3_13
  486. #define INIT_MSVD_COMB_CbGAIN        0x88     //BK3_14
  487. #define INIT_MSVD_COMB_CrGAIN       0x80// 0x80     //BK3_15
  489. #define INIT_MSVD_COMB_CONTRAST            0x94//0x9A  //BK3_63
  490. #define INIT_MSVD_COMB_BRIGHTNESS        0x96  //BK3_64
  491. #define INIT_MSVD_COMB_SATURATION        0x90//0xA0  //BK3_65
  492. #define INIT_MSVD_TV_BRIGHTNESS         0x0CE        // bk2_38[6] bk2_3a[7:0] MAXVALUE=0X1FF
  495. #ifdef EnableUseGammaTbl
  496. BYTE code tGammaTableNormal[3][33]=
  497. {
  498.         {
  499.                 0x00,0x03,0x07,0x0C,0x12,0x19,0x20,0x28,0x31,0x3A,0x43,
  500.                 0x4D,0x57,0x61,0x6B,0x75,0x80,0x8B,0x95,0x9F,0xA9,0xB3,
  501.                 0xBD,0xC6,0xCF,0xD7,0xDF,0xE6,0xEC,0xF2,0xF7,0xFB,0xFF,
  502.         },
  503.         {
  504.                 0x00,0x03,0x07,0x0C,0x12,0x19,0x20,0x28,0x31,0x3A,0x43,
  505.                 0x4D,0x57,0x61,0x6B,0x75,0x80,0x8B,0x95,0x9F,0xA9,0xB3,
  506.                 0xBD,0xC6,0xCF,0xD7,0xDF,0xE6,0xEC,0xF2,0xF7,0xFB,0xFF,
  507.         },
  508.         {
  509.                 0x00,0x03,0x07,0x0C,0x12,0x19,0x20,0x28,0x31,0x3A,0x43,
  510.                 0x4D,0x57,0x61,0x6B,0x75,0x80,0x8B,0x95,0x9F,0xA9,0xB3,
  511.                 0xBD,0xC6,0xCF,0xD7,0xDF,0xE6,0xEC,0xF2,0xF7,0xFB,0xFF,
  512.         },
  513. };
  514. #endif
  516. #ifdef EnableColorMatrix
  517. short code tVideoColorCorrectionMatrix[][3]=
  518. {
  519.    0x0441,-0x0041, 0x0000, 0x0030, 0x039E, 0x0032,-0x0045, 0x0092,
  520.    0x03B3,-0x0369, 0x01AB,-0x051B, 0x0012,-0x01D9, 0x0777,-0x0378,
  521.   -0x0735, 0x017A, 0x019E,-0x026E, 0x0274, 0x0687,-0x07A6, 0x0280,
  522.   -0x0831, 0x0100,-0x0001, 0x0001,-0x0001, 0x0000,-0x0064,-0x0032,
  523. };
  525. #endif
  527. #ifdef _EnableFCC_
  528. RegUnitType code tInitializeFCC[] =
  529. {
  530.     /////////////////////////////////////////////////
  531.     // Initialize MACE  table
  532.     /////////////////////////////////////////////////
  533.     {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
  534.     {BK1_56_FCC_CB_1T, 0x74}, // FCC_
  535.     {BK1_57_FCC_CR_1T, 0x9B}, // FCC_
  536.     {BK1_58_FCC_CB_2T, 0x6E}, // FCC_
  537.     {BK1_59_FCC_CR_2T, 0xAC}, // FCC_
  538.     {BK1_5A_FCC_CB_3T, 0xA5}, // FCC_
  539.     {BK1_5B_FCC_CR_3T, 0x69}, // FCC_
  540.     {BK1_5C_FCC_CB_4T, 0x5A}, // FCC_
  541.     {BK1_5D_FCC_CR_4T, 0x9A}, // FCC_
  542.     {BK1_5E_FCC_CB_5T, 0x5A}, // FCC_
  543.     {BK1_5F_FCC_CR_5T, 0x75}, // FCC_
  544.     {BK1_60_FCC_CB_6T, 0xB0}, // FCC_
  545.     {BK1_61_FCC_CR_6T, 0x48}, // FCC_
  546.     {BK1_62_FCC_CB_7T, 0x64}, // FCC_
  547.     {BK1_63_FCC_CR_7T, 0xD8}, // FCC_
  548.     {BK1_64_FCC_CB_8T, 0x80}, // FCC_
  549.     {BK1_65_FCC_CR_8T, 0x80}, // FCC_
  550.     {BK1_66_FCC_CB_9T, 0x80},//0x88}, // FCC_
  551.     {BK1_67_FCC_CR_9T, 0x80},// FCC_  A0
  552.     {BK1_68_FCC_WIN1, 0xA6}, // FCC_
  553.     {BK1_69_FCC_WIN2, 0xBA}, // FCC_
  554.     {BK1_6A_FCC_WIN3, 0xFB}, // FCC_
  555.     {BK1_6B_FCC_WIN4, 0x73}, // FCC_
  556.     {BK1_6C_FCC_WIN5, 0xFB}, // FCC_
  557.     {BK1_6D_FCC_WIN6, 0xFB}, // FCC_
  558.     {BK1_6E_FCC_WIN7, 0xFF}, // FCC_
  559.     {BK1_6F_FCC_WIN8, 0x6A}, // FCC_
  560.     {BK1_70_FCC_WIN9, 0x00}, // FCC_
  561.     {BK1_71_FCC_Y_TH, 0xFF}, // FCC_
  562.     {BK1_72_FCC_K1K2, 0x60}, // FCC_
  563.     {BK1_73_FCC_K3K4, 0xFE}, // FCC_
  564.     {BK1_74_FCC_K5K6, 0xCB}, // FCC_
  565.     {BK1_75_FCC_K7K8, 0x85}, // FCC_
  566. //    {BK1_76_FCC_CTRL, 0x2F}, // FCC_
  567. //    {BK1_77_APP_CTRL, 0x7E}, // FCC_
  568.     {BK1_78_PEAK_BAND1, 0x1D}, // FCC_
  569.     {BK1_79_PEAK_BAND2, 0x58}, // FCC_
  570. //    {BK1_7A_LTI, 0x98}, // FCC_
  571.     {BK1_7D_CTI,0x78},
  572.     {BK1_7E_VIP_Y_CTRL,0x00},
  573.     {BK1_7F_MAX_PIX, 0x80}, // MAX_PIX
  574.     {BK1_80_MIN_PIX, 0x40}, // MIN_PIX
  575. //    {BK1_81_EGE_BAND1_POS,0x40},
  576. //    {BK1_82_EGE_BAND1_NEG,0x60},
  577. //    {BK1_84_EGE_BAND2_NEG,0x60},
  578. //    {BK1_85_M_BRI,0x08},
  579. //    {BK1_86_EGE_LTI_POS,0x10},
  580. //    {BK1_87_EGE_LTI_NEG,0x20},
  581. //    {BK1_88_YC_LPF,        0xBC},
  582.     {BK1_89,        0x00},
  583. //    {BK1_8A,        0x23},
  584.     {BK1_8B,        0x43},
  585.     {BK1_8C, 0xFF},
  586.     {BK1_8D, 0xAE},
  587.     {BK1_8E, 0x36},
  588.     {BK1_8F, 0x01},
  589.     {BK0_00_REGBK, REG_BANK_SCALER},
  591.     {_END_OF_TBL_, 0x00}
  592. };
  594. RegUnitType code tVideoFCC[] =
  595. {
  596.     {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
  598.     {BK1_77_APP_CTRL, 0x00}, //7E FCC_
  599.     {BK1_85_M_BRI,0x00},
  600.     {BK1_88_YC_LPF,        0xBC},    //0xBC
  602.     {BK0_00_REGBK, REG_BANK_SCALER},
  604.     {_END_OF_TBL_, 0x00}
  605. };
  607. #if VGA_ENABLE
  608. RegUnitType code tPCFCC[] =
  609. {
  610.     {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
  612.     {BK1_77_APP_CTRL, 0}, // FCC_
  613.     {BK1_85_M_BRI,0},
  614.     {BK1_88_YC_LPF,        0},
  616.     {BK0_00_REGBK, REG_BANK_SCALER},
  618.     {_END_OF_TBL_, 0x00}
  619. };
  620. #endif
  622. RegUnitType code t_AVInitializeFCC[] =
  623. {
  624.     {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
  625.     {BK1_76_FCC_CTRL, 0x6F}, // FCC_
  626.     {BK1_7A_LTI, 0x98}, // FCC_
  627.     {BK1_7C_CROING,0x42},
  628.     {BK1_81_EGE_BAND1_POS,0x40},
  629.     {BK1_82_EGE_BAND1_NEG,0x60},
  630.     {BK1_84_EGE_BAND2_NEG,0x60},
  631.     {BK1_86_EGE_LTI_POS,0x10},
  632.     {BK1_87_EGE_LTI_NEG,0x20},
  633.     {BK1_88_YC_LPF,        0x80},
  634.     {BK1_8A,        0x23},
  635.     {BK0_00_REGBK, REG_BANK_SCALER},
  637.     {_END_OF_TBL_, 0x00},
  638. };
  640. RegUnitType code t_SVInitializeFCC[] =
  641. {
  642.     {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
  643.     {BK1_7A_LTI, 0x08}, // FCC_
  644.     {BK1_7C_CROING,0xFF},
  645.     {BK0_00_REGBK, REG_BANK_SCALER},
  647.     {_END_OF_TBL_, 0x00},
  648. };
  650. RegUnitType code t_TVInitializeFCC[] =
  651. {
  652.     {BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
  653.     {BK1_76_FCC_CTRL, 0x2D},
  654.     {BK1_7A_LTI, 0x90},
  655.     {BK1_7C_CROING,0x42},
  656.     {BK1_81_EGE_BAND1_POS,0x00},
  657.     {BK1_82_EGE_BAND1_NEG,0x00},
  658.     {BK1_84_EGE_BAND2_NEG,0x00},
  659.     {BK1_86_EGE_LTI_POS,0x00},
  660.     {BK1_87_EGE_LTI_NEG,0x00},
  661.     {BK1_88_YC_LPF,        0x9C},
  662.     {BK1_8A,        0x43},
  663.     {BK0_00_REGBK, REG_BANK_SCALER},
  665.     {_END_OF_TBL_, 0x00},
  666. };
  668. #endif // _EnableFcc_
  670. #endif
/}Z0\ ,  
DNy1} 3wg  


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