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PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs
[size=6][b]PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs[/b][/size]
[i]Abstract: Using a wafer-level package (WLP) can reduce the overallsize and cost of your solution. However when using a WLP IC, the printedcircuit board (PCB) layout can become more complex and, if notcarefully planned, result in an unreliable design. This article presentssome PCB design considerations and general recommendations for choosinga 0.4mm- or 0.5mm-pitch WLP for your application.[/i]
A similar version of this article appeared in Korean on [url=http://www.eetkorea.com/articleLogin.do?artId=8800657209&fromWhere=/en/ART_8800657209_480203_TA_e28d4968.HTM&catId=480203&newsType=TA&pageNo=null&encode=e28d4968][i]EE Times Korea[/i][/url], December 8, 2011.
[size=3][b]Introduction[/b][/size]
When designing a system-level circuit, printed circuit board (PCB) realestate can come at a premium. One method of reducing a design's requiredPCB area is to use a smaller IC package, such as a wafer-level package(WLP). This can free up a lot of area on your PCB and can also save youin cost, if you plan accordingly.
WLPs are much smaller than their predecessors because the package isbuilt up directly on the silicon substrate and no bond wires are used.This in turn saves cycle time and packaging costs. However, to keep PCBcosts at a minimum, some layout considerations need to be taken. Thistutorial will present some general PCB layout guidelines to follow whenusing WLPs. These guidelines are provided as an aid for developing a PCBlayout design to increase the chance that your design can be reliablymanufactured.
[i][b]Note:[/b] 1mil = 1/1000in = 0.0254mm[/i]
[size=3][b]SMD and NSMD Pads[/b][/size]
Before any routing is started, the first consideration should be thedesign of the WLP footprint. The WLP drawing will provide most of theinformation (package dimensions, tolerances, pin-pitch) needed to createthe PCB footprint. Another aspect to consider when creating the WLPfootprint is the type of pad to use for the IC pins. The pad options aresolder mask defined (SMD) and nonsolder mask defined (NSMD), both shownin [b]Figure 1[/b].
[img]https://www.maximintegrated.com/en/images/appnotes/5283/5283Fig01.gif[/img]
[i]Figure 1. When creating the WLP footprint, consider the type of padyou want to use for the IC pins, either the solder mask defined (SMD) orthe nonsolder mask defined (NSMD).[/i]
The SMD pad uses, as the name suggests, a solder mask to define the padarea to which the solder ball will be soldered. This method reduces thelikelihood of the pad lifting during the soldering or desolderingprocess. The disadvantage, however, is that this method reduces theamount of copper surface area available for the solder ball connection,and reduces the space between adjacent pads. This limits the thicknessof the traces between pads and may affect the use of vias.
The NSMD pad uses copper to define the pad area to which the solder bumpwill be soldered. This method provides a larger surface area for thesolder ball connection and provides more clearance (compared to SMD)between pads, allowing for wider trace widths and more flexibility inthe use of vias. The downside of this method is that it is moresusceptible to pad lifting during the soldering and desolderingprocesses.
The most recommended pad type is NSMD. This pad type lends itself to abetter solder connection, allowing the solder joint to encapsulate thepad. When starting a PCB design with WLPs, both pad types should beconsidered and their pros and cons weighed with the target applicationin mind. Note that both methods can be used on a single WLP footprint.
[size=3][b]Pitch Size[/b][/size]
Maxim offers a wide array of WLP ICs that are available in a 0.4mm or0.5mm pitch. The pitch size refers to the distance between the solderballs (i.e., pins) on the IC. The distance is measured fromcenter-to-center of two adjacent solder balls. The larger the pitch, themore space there is between pads to route traces.
A 0.5mm-pitch design offers a little more breathing room than itssmaller counterpart, the 0.4mm. The 0.5mm pitch gives you approximately19.7 mils of space between solder balls from center-to-center. A typicalpad size is 8.7 mils, giving you 11 mils between pads to route traces.Using a trace-to-solder-ball clearance of 3.5 mils, you can comfortablyfit a maximum trace width of approximately 4 mils between two definedsolder ball pads. With a 4-mil trace using 1oz copper (Cu), you arelimited to approximately 220mA current through the trace. With 2oz Cu,you can drive 380mA through a 4-mil trace. The spacing and dimensionsfor a 0.5mm-pitch WLP are shown in [b]Figure 2[/b]. For an example of a 0.5mm-pitch WLP PCB layout, refer to the [url=https://www.maximintegrated.com/en/MAX8896EVKIT]MAX8896 evaluation (EV) kit data sheet[/url] on Maxim's website.
[img]https://www.maximintegrated.com/en/images/appnotes/5283/5283Fig02.gif[/img]
[i]Figure 2. Spacing and dimensions for a 0.5mm-pitch WLP.[/i]
A 0.4mm (15.7-mil) pitch design can be a bit trickier than a 0.5mmdesign. There is a lot less space to route traces between solder balls,which means more restriction and less flexibility. A typical pad size is7 mils, leaving you with 8.7 mils between pads to route traces. Whenusing a 3-mil space on each side of an inner trace, you are only leftwith a maximum trace width of ~2.7 mils. The spacing and dimensions for a0.4mm-pitch WLP are shown in [b]Figure 3[/b]. With a 2.7-mil traceusing 1oz copper (Cu), you are limited to approximately 160mA currentthrough the trace. For smaller pitch such as 0.4mm, using thicker coppercan be a concern, since the trace width is less than the copper width(e.g. 2oz Cu = 2.8 mils). This can result in a net trace width of lessthan 2.7 mils after the etching/plating process. [b]Table 1[/b] provides a recommendation of trace width to copper thickness from a common PCB fab house.
[img]https://www.maximintegrated.com/en/images/appnotes/5283/5283Fig03.gif[/img]
[i]Figure 3. Spacing and dimensions for a 0.4mm-pitch WLP.[/i]
[table][tr][td=3,1]Table 1. Recommended Trace Widths[/td][/tr][tr][td]Copper Weight[/td][td]Copper Thickness[/td][td]Recommended Trace Width[/td][/tr][tr][td]0.5oz[/td][td]0.7 mils[/td][td]3 mils to 5 mils[/td][/tr][tr][td]1oz[/td][td]1.4 mils[/td][td]4 mils to 7 mils[/td][/tr][tr][td]2oz[/td][td]2.8 mils[/td][td]8 mils to 10 mils[/td][/tr][/table]
[size=3][b]Routing Alternatives[/b][/size]
If using a thinner trace between WLP pads does not work for your design,as is such for smaller-pitch WLPs (i.e., 0.3mm), other options can beused, but they each have their own disadvantages. One option is to use alaser-drilled via, which comes at a premium PCB cost. A laser-drilledvia is needed because mechanical drills have equipment limitations (likea 10-mil minimum drill-bit size), and because of the spacingconstraints between adjacent and diagonal pads of the WLP IC footprint.Laser-drilling is a PCB fab process where a via is laser-drilleddirectly into or offset from the WLP pad and then refilled, allowing atrace to be run on an inner layer. If you have an application where thePCB already uses a laser-drilled via (such as high-end audioapplications or cell phones), then the PCB cost may not be an issue.However, if you have an application where the PCB must be lower cost(like for some LCD displays), then the extra cost may not be justified.
Another less common alternative is to use a staggered-bump-array WLP. Bystaggering the balls on the WLP chip, you can create more room to routelarger traces. Not all WLP chips offer the luxury of staggered bumparrays, and this will need to be carefully planned during the initialstages of your design. Alternatively, you can use a WLP bump array thatis missing a few inner/outer pins. This will also give you more space toeither drop in a via or route a larger trace to the inner layers. Againthis will need to be carefully thought out very early in your design,while also considering any possible second source requirements for yourpart.
[size=3][b]Conclusion[/b][/size]
In this tutorial, some basic guidelines and design considerations havebeen presented to aid in the design of a PCB layout when using 0.4mm-and 0.5mm-pitch WLP ICs. The pad type (SMD and NSMD), allowable maximumtrace widths between pads, and alternatives to routing between pads(laser vias, staggered-array WLP, etc.) have been discussed to raiseawareness when designing with WLPs.
[i]Abstract: Using a wafer-level package (WLP) can reduce the overallsize and cost of your solution. However when using a WLP IC, the printedcircuit board (PCB) layout can become more complex and, if notcarefully planned, result in an unreliable design. This article presentssome PCB design considerations and general recommendations for choosinga 0.4mm- or 0.5mm-pitch WLP for your application.[/i]
A similar version of this article appeared in Korean on [url=http://www.eetkorea.com/articleLogin.do?artId=8800657209&fromWhere=/en/ART_8800657209_480203_TA_e28d4968.HTM&catId=480203&newsType=TA&pageNo=null&encode=e28d4968][i]EE Times Korea[/i][/url], December 8, 2011.
[size=3][b]Introduction[/b][/size]
When designing a system-level circuit, printed circuit board (PCB) realestate can come at a premium. One method of reducing a design's requiredPCB area is to use a smaller IC package, such as a wafer-level package(WLP). This can free up a lot of area on your PCB and can also save youin cost, if you plan accordingly.
WLPs are much smaller than their predecessors because the package isbuilt up directly on the silicon substrate and no bond wires are used.This in turn saves cycle time and packaging costs. However, to keep PCBcosts at a minimum, some layout considerations need to be taken. Thistutorial will present some general PCB layout guidelines to follow whenusing WLPs. These guidelines are provided as an aid for developing a PCBlayout design to increase the chance that your design can be reliablymanufactured.
[i][b]Note:[/b] 1mil = 1/1000in = 0.0254mm[/i]
[size=3][b]SMD and NSMD Pads[/b][/size]
Before any routing is started, the first consideration should be thedesign of the WLP footprint. The WLP drawing will provide most of theinformation (package dimensions, tolerances, pin-pitch) needed to createthe PCB footprint. Another aspect to consider when creating the WLPfootprint is the type of pad to use for the IC pins. The pad options aresolder mask defined (SMD) and nonsolder mask defined (NSMD), both shownin [b]Figure 1[/b].
[img]https://www.maximintegrated.com/en/images/appnotes/5283/5283Fig01.gif[/img]
[i]Figure 1. When creating the WLP footprint, consider the type of padyou want to use for the IC pins, either the solder mask defined (SMD) orthe nonsolder mask defined (NSMD).[/i]
The SMD pad uses, as the name suggests, a solder mask to define the padarea to which the solder ball will be soldered. This method reduces thelikelihood of the pad lifting during the soldering or desolderingprocess. The disadvantage, however, is that this method reduces theamount of copper surface area available for the solder ball connection,and reduces the space between adjacent pads. This limits the thicknessof the traces between pads and may affect the use of vias.
The NSMD pad uses copper to define the pad area to which the solder bumpwill be soldered. This method provides a larger surface area for thesolder ball connection and provides more clearance (compared to SMD)between pads, allowing for wider trace widths and more flexibility inthe use of vias. The downside of this method is that it is moresusceptible to pad lifting during the soldering and desolderingprocesses.
The most recommended pad type is NSMD. This pad type lends itself to abetter solder connection, allowing the solder joint to encapsulate thepad. When starting a PCB design with WLPs, both pad types should beconsidered and their pros and cons weighed with the target applicationin mind. Note that both methods can be used on a single WLP footprint.
[size=3][b]Pitch Size[/b][/size]
Maxim offers a wide array of WLP ICs that are available in a 0.4mm or0.5mm pitch. The pitch size refers to the distance between the solderballs (i.e., pins) on the IC. The distance is measured fromcenter-to-center of two adjacent solder balls. The larger the pitch, themore space there is between pads to route traces.
A 0.5mm-pitch design offers a little more breathing room than itssmaller counterpart, the 0.4mm. The 0.5mm pitch gives you approximately19.7 mils of space between solder balls from center-to-center. A typicalpad size is 8.7 mils, giving you 11 mils between pads to route traces.Using a trace-to-solder-ball clearance of 3.5 mils, you can comfortablyfit a maximum trace width of approximately 4 mils between two definedsolder ball pads. With a 4-mil trace using 1oz copper (Cu), you arelimited to approximately 220mA current through the trace. With 2oz Cu,you can drive 380mA through a 4-mil trace. The spacing and dimensionsfor a 0.5mm-pitch WLP are shown in [b]Figure 2[/b]. For an example of a 0.5mm-pitch WLP PCB layout, refer to the [url=https://www.maximintegrated.com/en/MAX8896EVKIT]MAX8896 evaluation (EV) kit data sheet[/url] on Maxim's website.
[img]https://www.maximintegrated.com/en/images/appnotes/5283/5283Fig02.gif[/img]
[i]Figure 2. Spacing and dimensions for a 0.5mm-pitch WLP.[/i]
A 0.4mm (15.7-mil) pitch design can be a bit trickier than a 0.5mmdesign. There is a lot less space to route traces between solder balls,which means more restriction and less flexibility. A typical pad size is7 mils, leaving you with 8.7 mils between pads to route traces. Whenusing a 3-mil space on each side of an inner trace, you are only leftwith a maximum trace width of ~2.7 mils. The spacing and dimensions for a0.4mm-pitch WLP are shown in [b]Figure 3[/b]. With a 2.7-mil traceusing 1oz copper (Cu), you are limited to approximately 160mA currentthrough the trace. For smaller pitch such as 0.4mm, using thicker coppercan be a concern, since the trace width is less than the copper width(e.g. 2oz Cu = 2.8 mils). This can result in a net trace width of lessthan 2.7 mils after the etching/plating process. [b]Table 1[/b] provides a recommendation of trace width to copper thickness from a common PCB fab house.
[img]https://www.maximintegrated.com/en/images/appnotes/5283/5283Fig03.gif[/img]
[i]Figure 3. Spacing and dimensions for a 0.4mm-pitch WLP.[/i]
[table][tr][td=3,1]Table 1. Recommended Trace Widths[/td][/tr][tr][td]Copper Weight[/td][td]Copper Thickness[/td][td]Recommended Trace Width[/td][/tr][tr][td]0.5oz[/td][td]0.7 mils[/td][td]3 mils to 5 mils[/td][/tr][tr][td]1oz[/td][td]1.4 mils[/td][td]4 mils to 7 mils[/td][/tr][tr][td]2oz[/td][td]2.8 mils[/td][td]8 mils to 10 mils[/td][/tr][/table]
[size=3][b]Routing Alternatives[/b][/size]
If using a thinner trace between WLP pads does not work for your design,as is such for smaller-pitch WLPs (i.e., 0.3mm), other options can beused, but they each have their own disadvantages. One option is to use alaser-drilled via, which comes at a premium PCB cost. A laser-drilledvia is needed because mechanical drills have equipment limitations (likea 10-mil minimum drill-bit size), and because of the spacingconstraints between adjacent and diagonal pads of the WLP IC footprint.Laser-drilling is a PCB fab process where a via is laser-drilleddirectly into or offset from the WLP pad and then refilled, allowing atrace to be run on an inner layer. If you have an application where thePCB already uses a laser-drilled via (such as high-end audioapplications or cell phones), then the PCB cost may not be an issue.However, if you have an application where the PCB must be lower cost(like for some LCD displays), then the extra cost may not be justified.
Another less common alternative is to use a staggered-bump-array WLP. Bystaggering the balls on the WLP chip, you can create more room to routelarger traces. Not all WLP chips offer the luxury of staggered bumparrays, and this will need to be carefully planned during the initialstages of your design. Alternatively, you can use a WLP bump array thatis missing a few inner/outer pins. This will also give you more space toeither drop in a via or route a larger trace to the inner layers. Againthis will need to be carefully thought out very early in your design,while also considering any possible second source requirements for yourpart.
[size=3][b]Conclusion[/b][/size]
In this tutorial, some basic guidelines and design considerations havebeen presented to aid in the design of a PCB layout when using 0.4mm-and 0.5mm-pitch WLP ICs. The pad type (SMD and NSMD), allowable maximumtrace widths between pads, and alternatives to routing between pads(laser vias, staggered-array WLP, etc.) have been discussed to raiseawareness when designing with WLPs.
