【英伟达NVIDIA】上海研发中心招聘芯片验证 / SOC / 后端 / CA

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公司简介：
NVIDIA 公司是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者，总部位于美国加利福尼亚州的圣克拉拉市，在20多个国家和地区拥有5700名员工。公司在可编程图形处理器方面拥有先进的专业技术，在并行处理方面实现了诸多突破。
工作地址：上海浦东新区秋月路26号
简历投递邮箱：heatherl@nvidia.com，简历请以附件形式发送
目前在招岗位列表如下：

[li]Physical Design CAD Engineer[/li][li]ASIC Physical Design Engineer[/li][li]Senior ASIC Design Verification Engineer[/li][li]ASIC Verification Engineer[/li][li]SOC Design Engineer[/li]

> Physical Design CAD Engineer
岗位职责：
1. Develop the physical design flow and methodology for allchips in NVIDIA (GeForce®/Tegra™/Tesla™/Quadro™).
2. Work with EDA vendors on tools evaluation and improvement.
3. Develop inhouse tools and solutions.
4. Support the global physical design team.
要求：
1. 电子/通信/计算机相关专业本科及以上学历
2. 具备任一领域专业经验：Floorplan, Place & Route, STA, layoutDRC/LVS, DFT, circuit design, RTL.
3. 编程能力强
加分项：
1. 熟悉Perl/TCL/Shell等脚本语言
2. 具有超大规模集成电路设计开发经验
3. 了解EDA工具：(ICC/DC/PT/STAR-RC/Astro/PC/Talus),Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) 等
> ASIC Physical Design Engineer
岗位职责：
1. Chip integration and netlist generation
2. Synthesis
3. Netlist quality check
4. Formal Verification
5. Constraints creation and validation, timing budget.
6. Co-work with PR engineers to implement chip partition and floorplan
7. Work in conjunction with RR engineers to achieve timing closure forboth partition and full chip level
8. Achieve special timing closure, such as io, test, clock etc.
9. Function eco creation
10. Develop and enhance entire timing closure flow from frontend (pre-layout)to backend (post-layout)
11. Flow automation development
12. Methodology in any of above areas.
要求：
1. 电子/通信/计算机相关专业本科及以上学历
2. 具备IC设计项目经验
3. 了解circuitdesign, digital design
4. 熟悉EDA 软件：Synopsys (DC/PT/Formality), Cadence (LEC)
加分项：
1. 熟悉Perl/TCL等脚本语言
2. 英文能力强
> Senior ASIC Design Verification Engineer
岗位职责：
1. You will participate in the research of verification methodology toimprove automation and productivity to produce Nvidia’s new high-quality stateof the art products.
2. Read IAS and design specs to understand the design requirement andbuild corresponding testplan. Review the testplan with arch/design engineers.
3. You responses to build block/IP testbench based on UVM methodology.
4. The responsibilities includes building test run and regression flow.Triage failures in regression and help designer root cause the bug.
5. Work includes Build various metrics (passing rate, functional coverage,etc) and monitor its health.
6. Take SOC verification on fullchip test environment for IPs
7. Analyse functional/code coverage result and identify the coverageholes. Work with design engineer to improve the coverage score.
8. Deploy the advanced verification methodology andinfrastructure of the SOC/IP
要求：
1. 电子/通信/计算机相关专业本科及以上学历
2. 硕士3年以上行业经验，本科5年以上行业经验
3. 熟悉UVM/VMM/OVM等验证方法，工具及流程
4. 熟悉验证流程，包括testplan,test, coverage model, testbench, BFM modeling.
5. 对Verilog andHVL语言有深入理解
加分项：
1. 掌握Perl ，C或C++ 语言
2. 有架构/设计相关经验
3. 掌握以下任一脚本语言 Shell,Ruby, Python
4. 良好的交流能力，分析能力和团队合作能力
> ASIC Verification Engineer
岗位职责：
1. Micro-architecture definition for System-level modules (Reset, Fuse,Strap, In-silicon measurement, Floorsweep, etc…)
2. RTL design, synthesis, timing and silicon bring-up
3. Unit-level and System-level verification
4. Chip level integration
要求：
1. 电子/通信/计算机相关专业本科及以上学历
2. 熟悉验证方法，工具及流程
3. 熟悉ASIC前端包括： RTL design, synthesis，timinganalysis
加分项：
1. 具备以下知识背景：Videotechniques, SOC architecture and Computer architecture
2. 掌握Perl ，C或C++ 语言
3. 良好的交流能力，分析能力和团队合作能力
> SOC Design Engineer
岗位职责：
The NVIDIA System-On-Chip (SOC) group is looking for a top SOC engineer with an interest in RTL integration and design as well as verification. The ideal candidate for this position has great passion for methodologies and automation solutions that enable creating SOCs in the least amount of time.
In this position, you will have the opportunity to be responsible for creating complex GPUs and SOCs and interface directly with unit-level, Physical Design, CAD, Package Design, Software, DFT and other teams. Additionally, you will be involved with defining and creating methodologies that create more efficient and flexible SOCs in future.
要求：
1. BS or MS (preferred) in EE or CS
2. Understand frontend ASIC design/verification/implementation flow
3. Excellent analytical and problem-solving skills
4. Strong coding skills in Perl or other industry-standard scripting languages
5. Fluent English (both written and spoken) and excellent communication skills to interface with many groups and build consensus
6. Good team work spirit, easy to cooperate with team members
7. Prior experience in implementing System-On-Chip is a plus
8. Prior experience in RTL build and design automation is a plus
工作地址：上海浦东新区秋月路26号

小丫

7790996

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