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最近写的一个SRAM控制器verilog格式 不对的地方高人多指点
控制外部SRAM需要注意什么?: Y( H; B( v. ]3 w5 ~* LF. v4 F
在代码风格上如何描述更稳定可靠呢?
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module SRAM_TEST(
i_Reset_n,
i_Clock,
i_EN," R' y1 y( @2 gy' A5 G
i_StepByStep,
i_WR_Control,# T. u( s( t9 e/ R% |4 c
o_W_FullSign,
/* SRAM Interface */
o_Sram_add,
io_Sram_data,
o_Sram_CE_n,
o_Sram_WE_n,
o_Sram_OE_n,2 Q) L7 Y% [+ B
o_Sram_UB_n,& D7 y0 Ys* d7 E+ Y
o_Sram_LB_n,' S9 D2 _7 E( b! l5 V2 _. A
/* Display */P2 H6 q' F* S4 l8 H
o_HEX," i1 ^1 N7 n. G- w, K
t_HEX);
input i_Reset_n;# L! Y: w$ h/ ]" b2 T
input i_Clock; 4 S& m2 A0 A1 z. W2 G
input i_EN;& \. f9 j" s3 ?! ]
input i_StepByStep;
input i_WR_Control;7 |# b7 ^+ N+ j/ A( i
output o_W_FullSign;6 [JB: _. H
/*SRAM Interface*/
output [17:0]o_Sram_add;, w" d, P- W1 }" e$ d$ ~6 A* D: a1 M
inout [15:0]io_Sram_data;
output o_Sram_CE_n;9 P# d( W% }' }^0 {/ g+ Q
output o_Sram_WE_n;- v, G/ l: {$ E4 j/ F
output o_Sram_OE_n;
output o_Sram_UB_n;
output o_Sram_LB_n;
/* Display */
output [6:0]o_HEX;C1 b_0 G1 W9 t) L0 [
output [6:0]t_HEX;1 z+ x, [1 F; V5 [) P$ u/ ?
reg [6:0]o_HEX;
reg [6:0]t_HEX;+ _- l7 v/ C8 }
reg [17:0] o_Sram_add;Q/ i- P! e8 m1 U6 i6 `" s
reg [3:0]t_counter;
reg o_Sram_CE_n;% _0 r2 _. j# D! C+ O/ W
reg o_Sram_WE_n;
reg o_Sram_OE_n;
reg o_Sram_UB_n;
reg o_Sram_LB_n;7 \# E% ~- H, z% d& A. V; C& F
reg [15:0] Sram_data_in;# p4 V5 W5 F) X( D4 ?" {/ O. S
reg [15:0] Sram_data_out;
reg Counter_EN;
reg [17:0] WADD_Counter; 5 T* h% f2 }& X( g" }! U! t
reg [17:0] RADD_Counter; : W$ T& J9 K6 B' ~: `9 l' B( J
reg [15:0] W_data;& |! B6 t" r4 C- |1 p2 t
reg o_W_FullSign;
reg [2:0]Sram_State;
reg i_StepByStep1;- i0 Q) T- o' J# A1 V9 h
reg i_StepByStep2;/ x+ FjZ9 q* I1 E
reg i_StepByStep3;% O/ L3 n- |. C& l# _
reg i_StepByStep4;$ Z& [! u0 ~x( q3 S2 @
reg i_WR_Control1;5 \$ B# w6 h8 @6 B2 e2 w
reg i_WR_Control2;! l& wr8 `+ M
reg i_WR_Control3; 5 q1 i6 e! S) b0 O2 k) ~6 C
always @(posedge i_Clock or negedge i_Reset_n): Z$ [$ R/ L# q$ v) ?. ]- @" e
if(~i_Reset_n)
Counter_EN<=0;
else begin 7 `. T, o! Mj- S1 d3 p
if(i_EN)
Counter_EN<=0;( ?* f. [! v/ [9 L/ ^d7 [
else, [% v2 q* `* M/ q
Counter_EN<=~Counter_EN;
end5 z. t8 I2 B; ]1 g5 C* _
# v+ [! S& {$ Y0 U$ J
always @(posedge i_Clock or negedge i_Reset_n)begin 6 w1 [, C/ b9 D9 j- x1 f1 f
if(~i_Reset_n)begin
i_StepByStep1<=1; 5 H; M) [" a' T' F1 Q- Q
i_StepByStep2<=1;* O" e5 ?- G, H0 C4 t1 b) ]/ e. X
i_StepByStep3<=1;
i_StepByStep4<=0;1 ?* I, v" ~" X
i_WR_Control1<=1; 7 K$ H6 o8 m4 O3 F" j3 P; xI
i_WR_Control2<=1;
i_WR_Control3<=1;o: z4 [4 q- G8 L, w. a% W6 p' `
end
else begin 8 s+ V8 J( Y{& x0 ]
i_StepByStep1<=i_StepByStep;
i_StepByStep2<=i_StepByStep1;
i_StepByStep3<=i_StepByStep2;2 _4 `; P5 uaW: Z8 W- Q4 R{
i_StepByStep4<=(i_StepByStep2 ^ i_StepByStep3) & i_StepByStep3;
i_WR_Control1<=i_WR_Control;
i_WR_Control2<=i_WR_Control1;6 c0 ^3 p% u9 L4 L/ c
i_WR_Control3<=i_WR_Control2;+ z. x, R0 i6 Q( J' x, {
end
end 6 T# [$ U" c$ b9 Z3 e
always @(posedge i_Clock or negedge i_Reset_n) 9 f/ d, g& }9 O& ?$ o
if(~i_Reset_n)begin
WADD_Counter<=0;- O1 L0 f: ~5 Y) k9 J
o_W_FullSign<=1;8 R5 R. h$ I7 s2 C
end9 f. R6 h% ^$ K" ]
else begin, T; U; C( M9 y6 z! ~9 i
if(i_WR_Control3 &i_StepByStep4==1)+ vh2 L( Y7 qg3 ?% K
if(WADD_Counter==15)begin& ]) N; n4 K8 l) D6 k+ M+ T0 r
WADD_Counter<=WADD_Counter;
o_W_FullSign<=0;
end7 X+ ^: }) i5 f! I) u
else begin
WADD_Counter<=WADD_Counter+1;% N; n7 O0 Z5 i0 T
o_W_FullSign<=o_W_FullSign;5 H9 \3 di. }: g
end
else begin
WADD_Counter<=WADD_Counter;
o_W_FullSign<=o_W_FullSign;
end& T. Z& K) W, S, y/ K3 T1 d: h
end
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always @(posedge i_Clock or negedge i_Reset_n)
if(~i_Reset_n)begin
W_data<=0;
end & u4 c; L" ul1 J2 e/ [
else begin
if(i_WR_Control3 &i_StepByStep4==1)
if(W_data==15)
W_data<=W_data;
else1 \# k% Q/ F$ i# g; ]4 j
W_data<=W_data+1;
else
W_data<=W_data;
end
always @(posedge i_Clock or negedge i_Reset_n)
if(~i_Reset_n)
RADD_Counter<=15;( x( F; D/ l/ `! @3 I8 @4 J* p- s! z
else begin) E, r3 m/ @7 G# k3 Y4 u
if(i_StepByStep4==1 & ~i_WR_Control3)
if(RADD_Counter==0)2 ?" |9 p& f( h3 s# r0 v
RADD_Counter<=15;( S( {( ], A6 w( g/ k" S2 J/ n
else1 s# o* C7 [4 t9 Q' ?
RADD_Counter<=RADD_Counter-1;; E! @5 s- l( }9 P/ H6 ?
else
RADD_Counter<=RADD_Counter;
end$ V9 ^# R( k: H7 c. M6 T7 L6 Y1 H: w. k
parameter IDLE =3'b000;4 I8 {6 {! j; }7 {, M
parameter READ =3'b001;
parameter WRITE =3'b010;
always @(posedge i_Clock or negedge i_Reset_n)* f, q, L! [) D' ^8 ]6 c7 p
if(~i_Reset_n)begin
Sram_State<=IDLE;( L1 S! s, F" F, k7 @4 i+ d! ~
o_Sram_add<={16{1'b0}};
Sram_data_in<={16{1'b0}};
Sram_data_out<={16{1'b0}};
o_Sram_CE_n<=1;1 w7 S% D& K% b6 [2 y( I
o_Sram_WE_n<=1;
o_Sram_OE_n<=1;. C& z/ z3 Q! j# n2 c
o_Sram_UB_n<=1;
o_Sram_LB_n<=1;7 Q3 u; C2 ?- Y7 u' O9 G8 O
end
else begin , Q0 r; U! }1 a
case(Sram_State)
IDLE:begin
if(~i_EN)begin
if(i_WR_Control3)begin
Sram_State<=WRITE;
o_Sram_add<=WADD_Counter; 5 I0 Z; {& @2 F( \4 _" P$ q
Sram_data_in<={16{1'bz}};
Sram_data_out<=Sram_data_out;: \! `( }2 N2 `8 w7 r1 [
o_Sram_CE_n<=0;
o_Sram_WE_n<=0;
o_Sram_OE_n<=1;
o_Sram_UB_n<=0;
o_Sram_LB_n<=0;; O$ M1 z2 g& O% E& T! S) X
end 4 a% Y/ ]5 `. o/ p7 N
else begin
Sram_State<=READ;
o_Sram_add<=RADD_Counter; ) g# \: \% w2 b6 `% z; @7 H
Sram_data_in<=Sram_data_in;
Sram_data_out<={16{1'bz}};
o_Sram_CE_n<=0;' Y: y# |5 |$ I8 G# ?+ N# U, ]
o_Sram_WE_n<=1;# j0 N, [: i; H7 F! U: }4 U- }# A7 ?
o_Sram_OE_n<=0;8 e' j$ |! R8 y3 k# Q9 V, v
o_Sram_UB_n<=0;% l* w: r& u1 O1 C5 ^
o_Sram_LB_n<=0;3 h# Y4 M& fx/ B) R( v9 E+ z* {
end
end
else begin
Sram_State<=IDLE;7 Y" M" f+ Y; {4 Y+ d- y
o_Sram_add<=0;0 u% D) I# z. X; K# ~
Sram_data_in<={16{1'b0}};9 H; A3 y; Y# w; \( q# X+ h
Sram_data_out<={16{1'b0}};
o_Sram_CE_n<=1;
o_Sram_WE_n<=1;
o_Sram_OE_n<=1;
o_Sram_UB_n<=1;
o_Sram_LB_n<=1;
end
end9 w# D+ `0 y8 l( {+ @; C4 w
READ:begin
Sram_State<=IDLE;
o_Sram_add<=RADD_Counter;
Sram_data_in<=io_Sram_data;. W: [1 d# h/ ^* f
Sram_data_out<={16{1'bz}};
o_Sram_CE_n<=0;5 h7 @, J# h/ I4 c; J' r; hO4 O- U
o_Sram_WE_n<=1;; e2 X; G/ H$ b! g8 t
o_Sram_OE_n<=0;0 F1 ?+ N" X: s- h/ V$ V
o_Sram_UB_n<=0;m, A; a7 F# B( I) o, o
o_Sram_LB_n<=0; 9 P# h) U7 v2 i6 K) d0 E9 ^# [
end # f- b" R8 N; h$ g( Y, S& |8 L
WRITE:begin6 K7 |- L' w) L0 V. w! ~
Sram_State<=IDLE;, r) x% U! }% X
o_Sram_add<=WADD_Counter; % b8 o+ D! _; Y6 J+ C# T. nr
Sram_data_in<={16{1'bz}};
Sram_data_out<=W_data;& y' g0 D1 Z" v( z5 l
o_Sram_CE_n<=0;
o_Sram_WE_n<=0;
o_Sram_OE_n<=1;
o_Sram_UB_n<=0;
o_Sram_LB_n<=0;
end5 [! b( a0 I) UU5 S: d; ~
default:begin% }: l# t9 xM6 w8 AC0 ~
Sram_State<=IDLE;
o_Sram_add<=0;
Sram_data_in<={16{1'bz}};
Sram_data_out<={16{1'bz}};/ h; y7 J8 ~; k5 ^* E; b
o_Sram_CE_n<=1;
o_Sram_WE_n<=1;
o_Sram_OE_n<=1;: c6 t- d; U2 c# u9 m1 iG
o_Sram_UB_n<=1;; ]0 `+ q: o# I3 z" V% a8 @1 c
o_Sram_LB_n<=1;
end
endcase
end; K. Q+ }: Y3 T& v' X8 n- a
assign io_Sram_data=(i_WR_Control3)? Sram_data_out:{16{1'bz}}; ' b; ~$ @) F4 p0 a; H
always @(posedge i_Clock or negedge i_Reset_n)
if(~i_Reset_n)
o_HEX<=7'b1000000;0 I5 F/ U6 n! z( G( \' V7 v
else begin
if(i_WR_Control3)
case(Sram_data_out[3:0])
4'b0000_HEX<=7'b1000000;
4'b0001_HEX<=7'b1111001;
4'b0010_HEX<=7'b0100100;/ \. I# l6 K1 f# |
4'b0011_HEX<=7'b0110000;3 U5 l4 f4 [" e1 V
4'b0100_HEX<=7'b0011001;1 U]% f# D; i# ?
4'b0101_HEX<=7'b0010010;
4'b0110_HEX<=7'b0000010;2 r' Q1 {) q+ W5 E; Z
4'b0111_HEX<=7'b1111000;
4'b1000_HEX<=7'b0000000;
4'b1001_HEX<=7'b0010000;
4'b1010_HEX<=7'b0001000;
4'b1011_HEX<=7'b0000011;
4'b1100_HEX<=7'b1000110;4 `1 t. r3 E9 Zn; _# W) m
4'b1101:o_HEX<=7'b0100001;# c& N2 T* o( R( U) q
4'b1110:o_HEX<=7'b0000110;
4'b1111:o_HEX<=7'b0001110;
default:o_HEX<=7'b1000000;- n, }f1 p% I
endcase $ [& R6 d4 |- H+ T6 z: N6 O
else
o_HEX<=7'b1000000;
end 9 t9 x" N8 Q" b$ \) K' z" y
always @(posedge i_Clock or negedge i_Reset_n)6 ~; ^+ [6 P3 b; W/ ?" {9 w2 E
if(~i_Reset_n)
t_HEX<=7'b1000000; + S2 Y3 _% z- n; q
else begin ( n5 @3 H) h1 T* LL4 T0 R9 \
case(Sram_data_in[3:0])% I$ a/ d7 P# Z2 i5 K% S; m
4'b0000:t_HEX<=7'b1000000;5 z: d9 X& F" T2 W% r- E
4'b0001:t_HEX<=7'b1111001;
4'b0010:t_HEX<=7'b0100100;+ i5 L7 O: \! T
4'b0011:t_HEX<=7'b0110000;
4'b0100:t_HEX<=7'b0011001;
4'b0101:t_HEX<=7'b0010010;
4'b0110:t_HEX<=7'b0000010;
4'b0111:t_HEX<=7'b1111000;
4'b1000:t_HEX<=7'b0000000;
4'b1001:t_HEX<=7'b0010000;
4'b1010:t_HEX<=7'b0001000;1 {3 u( r% B7 ~( c* Q
4'b1011:t_HEX<=7'b0000011;
4'b1100:t_HEX<=7'b1000110;& E% o) i! {* }! m3 Ja
4'b1101:t_HEX<=7'b0100001;
4'b1110:t_HEX<=7'b0000110;
4'b1111:t_HEX<=7'b0001110;; {) F% j6 h/ `p' a
default:t_HEX<=7'b1000000;
endcase
end
endmodule |
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