MC8051 IP core

2dmin

在网上寻找数字地与模拟地的英文材料；1 S- S( @5 EA4 w) b: y
无意间浏览到一个国外的的CPLD/FPGA论坛，点击进入$ \: l) [: ?( p( H8 i+ Q( c5 H
发现了有人求51的IP CORE，在回帖里面看到这个，所以下载了。

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@: mc8051@oregano.at
W: http://oregano.at/ip/8051.htm0 D& }& j8 ~* ^( v" u& h4 S

************************************************************
This is version 1.4 of the MC8051 IP core.% ^' R- m1 U3 g+ ^7 o
November 2004: Oregano Systems - Design & Consulting GesmbH- m# b: _6 I/ n6 {0 S. W; t
============================================================! v. U/ a& y/ u6 w1 \" d
Changes:I( r+ s& k% i, L; v" ]- F
- corrected behaviour of RETI instruction handling4 c6 H7 E4 j; w5 E. k( MW
- added synchronization for interrupt signals8 t, E7 F" G7 U. S* {$ w9 q
- corrected timer problems

************************************************************
This is version 1.3 of the MC8051 IP core.
September 2002: Oregano Systems - Design & Consulting GesmbH
============================================================9 D: _8 u; C* j1 \* w7 N" b
Change history:
- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.
- Corrected problem with duplex operation in file
mc8051_siu_rtl.vhd
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************************************************************
This is version 1.2. of the MC8051 IP core.6 M7 v0 F9 T- m! r
June 2002 - Oregano Systems - Design & Consulting GesmbH
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Change history:
- Eliminated the scr subdirectory form the distribution.0 r1 ]% J& n/ U) Z$ w: [* Y
- Improved documentation." o- ?1 k. t6 f3 c
- Corrected several bugs in the source code (see the0 d- G- S1 s3 j: z; H
website for more details).
- Improved the testbench with respect to the I/O port
behavior.+ p- [2 V8 s* o# T+ ^+ J
- Enriched the msim directory with the assembler source
code of an example program.
- Provided the source code of a Intel hex to binary
textfile converter to ease simulation of the user's
assambler programs.

************************************************************
This is version 1.1. of the MC8051 IP core.# W4 g; x; z2 J. Z" H. j, S7 d
Jan 31st 2002 - Oregano Systems - Design & Consulting GesmbH" W7 Z7 C* p1 `, H0 t
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下面是里面的部分VHDL+ \% t4 D8 D* k`9 Z2 B



library IEEE;
use IEEE.std_logic_1164.all; 7 V: o! w0 Q- w0 _% k5 Q
use IEEE.std_logic_arith.all;' W; C* L9 Z! |9 V% U: n
library work;
use work.mc8051_p.all;
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-----------------------------ENTITY DECLARATION--------------------------------) ^- o" q% J4 w( A! a+ [
entity addsub_core is
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generic (DWIDTH : integer := 16); -- Data width of the ALU9 c' U7 X, d2 \BX1 q& a
port (opa_i  : in std_logic_vector(DWIDTH-1 downto 0);5 j5 RN# _5 o) O/ B
  opb_i  : in std_logic_vector(DWIDTH-1 downto 0);0 ~6 ?. Y6 [6 I3 @. X
  addsub_i : in std_logic;* Y& l5 V9 P" |- AC, |1 |
  cy_i : in std_logic;
  cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
  ov_o : out std_logic;$ L% A! i) f, |* @( v4 G
  rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
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end addsub_core;' p3 V# E: h) s' o! Z

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entity mc8051_alu is
generic (DWIDTH : integer := 8);     -- Data width of the ALU4 J, |W3 y4 lT, [; e1 V: x! A
port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
  ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
  acc_i  : in std_logic_vector(DWIDTH-1 downto 0);5 X9 T3 Y7 u" b}7 ua' x* }( ?' g
  cmd_i  : in std_logic_vector(5 downto 0);
  cy_i   : in std_logic_vector((DWIDTH-1)/4 downto 0);; t7 Q$ x7 S( Z- a
  ov_i   : in std_logic;

  new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);[# ?, t* z+ eD8 ?; q! `
  new_ov_o : out std_logic;/ R]" Y. X5 s+ Z6 ^' R/ T, b
  result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
  result_b_o : out std_logic_vector(DWIDTH-1 downto 0));

end mc8051_alu;! X1 B% ?; G0 N
--Inputs:5 fV* w' [: L, N8 U1 r# W
-- rom_data_i...... data input from ROM
-- ram_data_i...... data input from RAM
-- acc_i........... the contents of the accumulator register9 B+ u3 f/ I9 ~
-- cmd_i........... command from the control unit
-- cy_i............ CY-Flags of the SFR
-- ov_i............ OV-Flag of the SFR
--Outputs:1 F% @2 @) i7 x8 ?
-- new_cy_o........ new CY-Flags for SFR
-- new_ov_o........ new OV-Flag for SFR8 w1 R8 Y0 Jn9 c+ _" f6 t
-- result_a_o...... result
-- result_b_o...... result) a8 \5 h2 t' ], |
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architecture struc of mc8051_alu is7 }: m6 K* j; h
signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);% ~6 z6 l0 E0 Q; W
signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);
signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0);# I7 J( a4 Z% f. b* ~3 \( R
signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);3 k/ p+ L9 l4 H2 {* b( c
signal s_alu_cmd  : std_logic_vector(3 downto 0);
signal s_dvdnd  : std_logic_vector(DWIDTH-1 downto 0);: |" l0 B' r! ^. I1 H5 F
signal s_dvsor  : std_logic_vector(DWIDTH-1 downto 0);& ~8 Q. P6 {& Q, j$ N' L
signal s_qutnt  : std_logic_vector(DWIDTH-1 downto 0);
signal s_rmndr  : std_logic_vector(DWIDTH-1 downto 0);
signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);
signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);+ F8 u* r& Q. P1 L- F( R) r
signal s_product  : std_logic_vector((DWIDTH*2)-1 downto 0);- D/ V6 j2 m8 @( v2 Z* M- @7 L
signal s_dcml_data  : std_logic_vector(DWIDTH-1 downto 0);( V( P; C, l! }! v8 c
signal s_dcml_rslt  : std_logic_vector(DWIDTH-1 downto 0);9 x7 {, r* [* i6 j! v! j' B
signal s_dcml_cy  : std_logic;& }3 j4 |( c# D# o3 H
signal s_addsub_rslt: std_logic_vector(DWIDTH-1 downto 0);+ f+ }* b! ]9 J8 U% [, uql
signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);
signal s_addsub_ov  : std_logic;; b- M0 g, p7 @% w3 c5 Y
signal s_addsub_cy  : std_logic;: ]. Cn% s/ ]' @0 L' M0 ], B- G
signal s_addsub   : std_logic;
signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);5 B9 {. b: }4 h* _+ n: Z; _
signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);6 t, A" i" C6 A2 Y$ [
begin     -- architecture structural
i_alumux : alumux. z. r1 k- I3 F1 e' C4 V7 x
  generic map (
  DWIDTH => DWIDTH)# v* B' y$ y+ F' r8 z0 Y
  port map (2 P/ {^/ N# P3 \
  -- Primary I/Os of the ALU unit.. P' i" M; C9 `1 z3 g' y
  rom_data_i  => rom_data_i,
  ram_data_i  => ram_data_i,
  acc_i   => acc_i,
  cmd_i   => cmd_i,
  cy_i    => cy_i,
  ov_i    => ov_i,$ {! Q* r8 o4 T6 w4 X
  cy_o    => new_cy_o,
  ov_o    => new_ov_o,
  result_a_o  => result_a_o,0 |" r7 t& M5 {! t0 M5 v9 ~' {
  result_b_o  => result_b_o,
  -- I/Os connecting the submodules.; t9 ^) R& ~8 v& \: `- |
  result_i  => s_alu_result,! b+ E& q; y7 G
  new_cy_i  => s_alu_new_cy,6 g8 Q6 A- j" P" \2 c2 l, e
  addsub_rslt_i => s_addsub_rslt,
  addsub_cy_i => s_addsub_newcy,
  addsub_ov_i => s_addsub_ov,; N, u: E; o6 A/ k) a
  op_a_o  => s_alu_op_a,
  op_b_o  => s_alu_op_b,( l; ]5 V$ c- z) F( ~
  alu_cmd_o => s_alu_cmd,
  opa_o   => s_addsub_opa,
  opb_o   => s_addsub_opb,2 ~' N9 Y/ a* i& ]K7 M1 ~
  addsub_o  => s_addsub,0 D) O) e- `4 F( S: _, l
  addsub_cy_o => s_addsub_cy,0 |! N" a+ j- H% n' O
  dvdnd_o   => s_dvdnd,+ w7 I) w& \/ \) g: G
  dvsor_o   => s_dvsor,/ F5 p* X6 s8 Z7 ]3 l5 q: F: {8 C
  qutnt_i   => s_qutnt,7 e% d' o; I1 B3 @' v1 n) Y" O
  rmndr_i   => s_rmndr,
  mltplcnd_o  => s_mltplcnd,1 L! W; S+ \; b4 g6 z
  mltplctr_o  => s_mltplctr,
  product_i => s_product,
  dcml_data_o => s_dcml_data,: Q9 W1 D& i3 L# A
  dcml_data_i => s_dcml_rslt,
  dcml_cy_i => s_dcml_cy);0 `0 S% [0 N; T- p7 Tt* C
i_alucore : alucore2 z8 `* r0 Q5 y' f. U
  generic map (
  DWIDTH  => DWIDTH)
  port map (" V; Z/ z" q# ?" L" u% p
  op_a_i  => s_alu_op_a,: C, [5 N6 ZY
  op_b_i  => s_alu_op_b,
  alu_cmd_i => s_alu_cmd,
  cy_i  => cy_i,8 ]( N+ p( [9 p6 e8 C/ z8 a
  cy_o  => s_alu_new_cy,- }9 n% M. cx/ ^) U6 o- s
  result_o=> s_alu_result);4 w: Q' R% Y2 u) d, I7 {
i_addsub_core : addsub_core
  generic map (DWIDTH => DWIDTH)
  port map (opa_i  => s_addsub_opa,
    opb_i  => s_addsub_opb,
    addsub_i => s_addsub,
    cy_i => s_addsub_cy,
    cy_o => s_addsub_newcy,
    ov_o => s_addsub_ov,0 N- F! v7 xT3 I/ i3 J6 E
    rslt_o => s_addsub_rslt);
gen_multiplier1 : if C_IMPL_MUL = 1 generate; T: {: ], l1 J7 O$ d5 G3 i' h% f$ h
  i_comb_mltplr : comb_mltplr
  generic map (
  DWIDTH => DWIDTH)- U2 d1 W# A8 ?) p: @+ B% I' Y
  port map (# Q9 ]. x2 |" G; k- sL5 d4 j5 ?* A
  mltplcnd_i => s_mltplcnd,( O, m7 p, J0 h8 A
  mltplctr_i => s_mltplctr,9 ^8 {# C; L) a' s6 H7 x
  product_o=> s_product);
end generate gen_multiplier1;
gen_multiplier0 : if C_IMPL_MUL /= 1 generate
  s_product <= (others => '0');. }" o( j, N' {# Q2 r" m
end generate gen_multiplier0;
gen_divider1: if C_IMPL_DIV = 1 generate) p3 CE, _; r6 E
  i_comb_divider : comb_divider
  generic map (% z- e( X% k0 q4 y4 V! Q4 u
  DWIDTH=> DWIDTH)( G- I* L9 T( K' m
  port map (4 p# f, |; K2 {0 X
  dvdnd_i => s_dvdnd,) O- x, l2 c) @1 t6 L/ X% U
  dvsor_i => s_dvsor,
  qutnt_o => s_qutnt,: x$ j# h+ P; }8 s. |6 r3 a
  rmndr_o => s_rmndr);7 g& R* N, C! |7 Y
end generate gen_divider1;# W) C$ i$ j- ]5 g
gen_divider0: if C_IMPL_DIV /= 1 generate6 p; ^9 [! ^/ `+ [& |
  s_qutnt <= (others => '0')" |: s, N* E; P: E~
  s_rmndr <= (others => '0');' R3 w5 c0 H5 E8 [" c: `8 o! O
end generate gen_divider0;6 C" M* @! P' F! c2 W
gen_dcml_adj1: if C_IMPL_DA = 1 generate
  i_dcml_adjust : dcml_adjust# M' @; u$ @" a, I8 ?
  generic map (8 @) b7 I1 P% v
  DWIDTH => DWIDTH)
  port map () Y1 r2 r, g- t) o5 n8 {1 x: m( p" y2 |
  data_i => s_dcml_data,
  cy_i => cy_i,; d/ r: R" q( q( e$ B$ [
  data_o => s_dcml_rslt,9 f1 U, {5 X1 ]. p
  cy_o => s_dcml_cy);6 O3 R$ U2 I/ k. u' w
end generate gen_dcml_adj1;
gen_dcml_adj0: if C_IMPL_DA /= 1 generate
  s_dcml_rslt <= (others => '0');
  s_dcml_cy <= '0';* D9 h" L" l0 {x3 OC
end generate gen_dcml_adj0;
end struc;










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