ZT: Startup breaks out with 3D PLDs - FPGA/CPLD - 电子工程师俱乐部

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Tabula Inc., a privately-held fabless semiconductor startup company founded November 2003, recently came out of "stealth mode" with the introduction of Spacetime, a novel programmable logic architecture that uses time as a third dimension to deliver capability and affordability unmatched by traditional FPGA.HTM" target="_blank">FPGA and CPLD architectures.

<i>Teig: I asked myself what if there was a new class of programmable device beyond FPGA.</i>

Tabula has raised about $106 million in venture capital and has 100 employees. Its staff includes veterans in the electronics industry such as Dennis Segers, CEO, who spent more than 10 years at Xilinx where he spearheaded the development and market entry of Virtex; Steve Teig, founder, president and chief technology officer, who comes from Cadence and is considered the inventor of modern place-and-route technology; and Daniel Gitlin, VP, manufacturing technology, who spent about 18 years at Xilinx and is responsible for Tabula gaining access to TSMC's 40nm technology in September 2007 during the early days of that node.
When at Cadence, Teig realized his customers were grappling with the expense of programmable devices or the expense and effort that goes into developing ASICs. It was here that he incubated the idea of Spacetime.
"As CTO of Cadence, I frequently observed just how expensive, time-consuming, and risky ASIC and ASSP tape-outs were becoming," said Teig. "I asked myself what if there was a new class of programmable device beyond FPGA: one with unprecedented capacity, memory, throughput, and performance at a price suitable for volume production. Such a device could displace not only FPGAs but also the vast majority of ASICs and ASSPs, finally delivering on the promise of programmable devices to change the whole digital logic landscape and not just a corner of it. After much effort, I realized that I could see how to build such a device, one that could help not only large companies but also two guys in a garage to design hardware quickly and inexpensively, getting into volume production without having to abandon programmability. I had to start a company."
<strong>Spacetime concept</strong>
The Spacetime technology uses time as a third dimension in programmable logic while maintaining a familiar design flow. Tabula calls the result a new class of programmable devices called 3PLDs (from 3D programmable logic devices), which they claim will deliver higher performance than traditional 40nm FPGAs.

<strong><i>Figure 1</i></strong><i>: Tabula claims its architecture delivers significant performance and logic density advantages over traditional FPGAs.</i>

"We are doing nothing exotic with the process," explained Alain Bismuth, VP, marketing. "We are using TSMC's standard 40nm process in a standard high-performance package—there is nothing like chip stacking or 3D silicon." Spacetime devices instead reconfigure on the fly at multi-gigahertz rates, executing each portion of a design in an automatically defined sequence of steps. Spacetime uses this ultra-rapid reconfiguration to make time a third dimension (Figure 1), resulting in a 3D device with multiple folds in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place.
By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an inherently 2D FPGA.
"Think of a user cycle as of 200MHz, which is a commonly used frequency in communications equipment," said Bismuth. "What we do is divide this clock cycle into [and up to] eight sub-cycles—so we have a sub-cycle clock running at 1.6GHz." The software automatically identifies which portion of the user circuit is executed during the first 1/8th of the user cycle, what portion is executed during the second 1/8th of the cycle and so on. The software then reconfigures the entire chip—logic and interconnect—for the first 1/8th of the circuit or what we call the first "fold" of this eight-storey chip.
"When this portion of the circuit is executed, the device is reconfigured to execute the second-eighth of the user functionality [using locally stored data] all the way to the eighth fold." Bismuth added that this is equivalent to achieving eight transistors of the 2D architecture with one transistor.
A device with eight folds is smaller than its equivalent 2D implementation and as a result, this 3D device has shorter interconnects. Spacetime also requires fewer resources for data interconnect and routing because narrower data paths are used compared to those found in FPGAs. An 8bit-wide path in eight folds, for instance, delivers 64bits that would require a 64bit data path in an FPGA.
Creating and managing folds is handled by the software and is transparent to the user. The architecture is delivered using a familiar methodology by the compiler that automatically maps standard RTL into Spacetime.
"The software can automatically identify which portion of the design runs at what speed and automatically assign the relevant sub-cycle clock frequency and the required number of fold," added Bismuth. "For example, say a design has three clock domains—100MHz, 200MHz and 800MHz. For the 100MHz clock domain, the software will automatically generate an 800MHz sub-cycle clock with eight folds. For the 200MHz, the software will generate a 1.6GHz sub-cycle clock with eight folds and for the 800MHz domain the software will automatically generate a 1.6GHz sub-cycle clock but this time there will only be two folds.

<strong><i>Figure 2: </i></strong><i>Spacetime architecture creates folds of circuit portions in time and running at frequencies up to 1.6GHz to allow trading of time with space and performance with density.</i>

In essence, we are trading space for time and density for performance. For example, you may have a critical task running at 400-600MHz. It normally occupies a very small portion of the overall design—3-5 percent. But the rest is running at a much more modest frequency. For the critical task you have to leave some density on the table—that's the Spacetime tradeoff in favor of performance. But for the bulk of the design running at 200MHz or below, you can achieve maximum folding thereby extracting the maximum density advantage.