Microsemi MPF300PolarFire FPGA图像和视频解决方案

jackywang

Microsemi公司的PolaRFIre™ FPGA是第五代非易失FPGA器件,采用28nm非易失工艺技术,采用业界最低功耗的FPGA构造,最低功耗12.7Gbps收发器通路,内置了低功耗双PCI Express Gen2 (EP/RP),以及可选择数据安全器件,低功耗加密协处理器.因此具有最佳的成本器件,并提供中等密度器件的最低功耗.PolarFire™ FPGA有多达481K逻辑单元,包括有可断裂D型触发器的4输入查找表(LUT),20Kb双或两端口大静态随机存储器(LSRAM)区块,64x12两端口区块,具有预加器,48位累加器的18x18数学区块,以及可选择16深x18系数ROM,高速串行连接性,内置了多吉比特和多协议收发器,速度从250Mbps到12.7 Gbps,高速I/O(HSIO)支持高达1600 Mbps DDR4, 1333 Mbps DDR3L和1333 Mbps,集成了I/O数字的LPDDR3/DDR3存储器,PolarFire™ FPGA工作在1.0V和1.05V电压,商用温度(0℃- 100℃) 和工业温度(–40℃-100℃).主要用在有线接入网(1G-40G),无线异构网络,无线骨干网,智能光模块以及视频广播.本文介绍了MPF300 PolarFire™ FPGA主要特性,框图和收发器通路模式图,评估板MPF300-VIDEO-KIT主要特性和框图,电路图和PCB设计图.

PolarFire™ FPGAs are the fifth-generation family of non-volatile FPGA devices from Microsemi, built onstate-of-the-art 28nm non-volatile process technology. Cost-optimized PolarFire FPGAs deliver thelowest power at mid-range densities. PolarFire FPGAs lower the cost of mid-range FPGAs by integratingthe industry’s lowest power FPGA fabric, lowest power 12.7 Gbps transceiver lane, built-in low powerdual PCI Express Gen2 (EP/RP), and, on select data security (S) devices, an integrated low-power crypto co-processor. PolarFire FPGAs can operate at 1.0 V and 1.05 V, offering the end user the ability to tradeoff power and performance to match the application requirements.

This document describes the features of the production PolarFire FPGA extended commercial(0℃ to100℃) and industrial (–40℃ to 100℃) device offerings. Please refer to the datasheet for current siliconstatus and electrical characteristics.

MPF300 PolarFire™ FPGA主要特性:

Up to 481K logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flipflop
20 Kb dual- or two-port large static random access memory (LSRAM) block with built-in single errorcorrect double error detect (SECDED)
64 × 12 two-port μRAM block implemented as an array of latches
18 × 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16 deep x 18 coefficientROM
Built-in μPROM, modifiable at program time, readable at run time for user data storage
High-speed serial connectivity with built-in multi-gigabit multi-protocol transceivers from 250 Mbpsto 12.7 Gbps
Integrated dual PCIe for up to ×4 Gen2 endpoint (EP) and root port (RP) designs
High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 Mbps
LPDDR3/DDR3 memories with integrated I/O digital
General purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 MbpsDDR3, and 1600 Mbps LVDS I/O speed with integrated I/O digital logic
Low-power phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low-jitterV and 1.05 V operating modes
Low-Power Features
Low device static power
Low inrush current
Low power transceivers
Reliability Features
FPGA configuration cells single event upset (SEU) immune
Built-in SECDED and memory interleaving on LSRAMs
System controller suspend mode for safety-critical designs
Security Features
Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bitstreamprotection
Integrated physically unclonable function (PUF)
56 KBytes of secure non-volatile memory (sNVM)
Built-in tamper detectors and countermeasures
Digest integrity check for FPGA, μPROM, and sNVM
Data security features in S devices—true random number generator, integrated Athena TeraFireEXP5200B Crypto Coprocessor, suite B capable, and CRI DPA countermeasure pass-through license
Libero® SoCPolarFire FPGA Toolset
Complete FPGA and embedded software development environment
Includes Synplify Pro synthesis and Mentor ModelSim ME simulation[sub][/sub][sup][/sup][strike][/strike]

sun5304

  

qiangzicong123

FPGA感觉很火啊

hsin

    

养步骗反

学习