tps51200DDR稳压

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23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUT3.3 VINPGOODSLP_S3VTTREFVLDOINVTTVDDQCopyright © 2016, Texas Instruments Incorporated ProductFolderOrderNowTechnicalDocumentsTools &SoftwareSupport &CommunityReferenceDesign本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。English Data Sheet: SLUS812TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020TPS51200 灌电流和拉电流 DDR 终端稳压器11 特性1• 输入电压：支持 2.5V 和 3.3V 电源轨• VLDOIN 电压范围：1.1V 至 3.5V• 具有压降补偿功能的灌电流和拉电流终端稳压器• 需要超小的输出电容 20μF（通常为 3 × 10μFMLCC），即可用于存储器终端 应用 (DDR)• 用于监视输出稳压的 PGOOD• EN 输入• REFIN 输入允许直接或通过电阻分压器灵活进行输入跟踪• 远程检测 (VOSNS)• ±10mA 缓冲基准 (REFOUT)• 内置软启动，欠压锁定 (UVLO) 和过流限制 (OCL)• 热关断• 支持 DDR、DDR2、DDR3、DDR3L、低功耗DDR3 和 DDR4 VTT 应用• 带有散热焊盘的 10 引脚超薄小外形尺寸无引线(VSON) 封装2 应用• 用于 DDR、DDR2、DDR3、DDR3L、低功耗DDR3 和 DDR4 的存储器终端稳压器• 笔记本、台式机和服务器• 电信和数据通信• 基站• 液晶 (LCD) 电视和等离子 (PDP) 电视• 复印机和打印机• 机顶盒3 说明TPS51200 器件是一款灌电流和拉电流双倍数据速率(DDR) 终端稳压器，专门针对低输入电压、低成本、低噪声的空间受限型系统而设计。TPS51200 可保持快速的瞬态响应，仅需 20μF 超低输出电容。TPS51200 支持遥感功能，并满足 DDR、DDR2、DDR3、DDR3L、低功耗 DDR3 和 DDR4VTT 总线终端的所有电源要求。此外，TPS51200 还提供一个开漏 PGOOD 信号来监测输出稳压，并提供一个 EN 信号在 S3（挂起至RAM）期间针对 DDR 应用对 VTT 进行放电。TPS51200 采用带散热焊盘的高效散热型 10 引脚VSON 封装，具有绿色环保和无铅的特性。其额定温度范围为 -40°C 至 +85°C。器件信息(1)器件型号 封装 封装尺寸（标称值）TPS51200 VSON (10) 3.00mm × 3.00mm(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。简化的 DDR 应用2TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated目录1 特性.......................................................................... 12 应用.......................................................................... 13 说明.......................................................................... 14 修订历史记录 ........................................................... 25 Pin Configuration and Functions......................... 36 Specifications......................................................... 46.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information.................................................. 46.5 Electrical Characteristics........................................... 56.6 Typical Characteristics .............................................. 77 Detailed Description ............................................ 107.1 Overview ................................................................. 107.2 Functional Block Diagram ....................................... 107.3 Feature Description................................................. 107.4 Device Functional Modes........................................ 168 Application and Implementation ........................ 178.1 Application Information............................................ 178.2 Typical Application ................................................. 178.3 System Examples ................................................... 209 Power Supply Recommendations...................... 2610 Layout................................................................... 2610.1 Layout Guidelines ................................................. 2610.2 Layout Example .................................................... 2710.3 Thermal Design Considerations............................ 2711 器件和文档支持 ..................................................... 2911.1 器件支持................................................................ 2911.2 文档支持 ............................................................... 2911.3 社区资源................................................................ 2911.4 商标....................................................................... 2911.5 静电放电警告......................................................... 2911.6 Glossary ................................................................ 2912 机械、封装和可订购信息....................................... 294 修订历史记录注：之前版本的页码可能与当前版本有所不同。Changes from Revision C (November 2016) to Revision D Page• Added "keep total REFOUT capacitance below 0.47 μF" in Pin Functions table ................................................................. 3Changes from Revision B (September 2016) to Revision C Page• 已添加 通篇添加了对 DDR3L DRAM 技术的引用................................................................................................................... 1• Added DDR3L test conditions to Output DC voltage, VO and REFOUT specification .......................................................... 5• Added Figure 4 ....................................................................................................................................................................... 7• Added Figure 9 ....................................................................................................................................................................... 8• Updated Figure 16 to include DDR3L data ............................................................................................................................ 9Changes from Revision A (September 2015) to Revision B Page• Changed " –10 mA < IREFOUT < 10 mA" to "–1 mA < IREFOUT < 1 mA" in all test conditions for the REFOUT voltagetolerance to VREFIN specification ............................................................................................................................................. 6• Changed all MIN and MAX values from "15" to "12" for all test conditions for the REFOUT voltage tolerance toVREFIN specification ................................................................................................................................................................. 6• Updated Figure 19 ............................................................................................................................................................... 11• Added REFOUT (VREF) Consideration for DDR2 Applications section................................................................................. 15• Updated Figure 28 and Table 3............................................................................................................................................ 20• Added clarity to Layout Guidelines section. ......................................................................................................................... 26Changes from Original (February 2008) to Revision A Page• 已添加 添加了引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ................................................................. 1• Changed “PowerPAD” references to “thermal pad” throughout ............................................................................................. 3• Deleted Dissipation Ratings table .......................................................................................................................................... 4REFIN 12345VLDOINVOPGNDVOSNS109876VINPGOODGNDENREFOUTThermalPad3TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated(1) I = Input, O = Output , G = Ground(2) Thermal pad connection. See Figure 35 in the Thermal Design Considerations section for additional information.5 Pin Configuration and FunctionsDRC Package10-Pin VSONTop ViewPin FunctionsPINI/O(1) DESCRIPTIONNAME NO.EN 7 IFor DDR VTT application, connect EN to SLP_S3. For any other application, use the EN pin as the ON/OFFfunction.GND 8 G Signal ground.PGND(2) 4 G Power ground for the LDO.PGOOD 9 O Open-drain, power-good indicator.REFIN 1 I Reference input.REFOUT 6 OReference output. Connect to GND through 0.1-μF ceramic capacitor. If there is a REFOUT capacitors at DDRside, keep total capacitance on REFOUT pin below 0.47 μF. The REFOUT pin can not be open.VIN 10 I 2.5-V or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is required.VLDOIN 2 I Supply voltage for the LDO.VO 3 O Power output for the LDO.VOSNS 5 I Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the load.4TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to the network ground terminal unless otherwise noted.6 Specifications6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)MIN MAX UNITInput voltage(2)REFIN, VIN, VLDOIN, VOSNS –0.3 3.6EN –0.3 6.5 VPGND to GND –0.3 0.3Output voltage(2) REFOUT, VO –0.3 3.6VPGOOD –0.3 6.5Operating junction temperature, TJ –40 150 °CStorage temperature, Tstg –55 150 °C(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.6.2 ESD RatingsVALUE UNITV(ESD)ElectrostaticdischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±5006.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)MIN NOM MAX UNITSupply voltages VIN 2.375 3.500 VVoltageEN, VLDOIN, VOSNS –0.1 3.5VREFIN 0.5 1.8PGOOD, VO –0.1 3.5REFOUT –0.1 1.8PGND –0.1 0.1Operating free-air temperature, TA –40 85 °C(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.6.4 Thermal InformationTHERMAL METRIC(1)TPS51200DRC (VSON) UNIT10 PINSRθJA Junction-to-ambient thermal resistance 55.6 °C/WRθJC(top) Junction-to-case (top) thermal resistance 84.6 °C/WRθJB Junction-to-board thermal resistance 30.0 °C/WψJT Junction-to-top characterization parameter 5.5 °C/WψJB Junction-to-board characterization parameter 30.1 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 10.9 °C/W5TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated(1) Ensured by design. Not production tested.6.5 Electrical CharacteristicsOver recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT= 3 × 10 μF and circuit shown in Figure 24. (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSUPPLY CURRENTIIN Supply current TA = 25 °C, VEN = 3.3 V, No Load 0.7 1 mAIIN(SDN) Shutdown currentTA = 25 °C, VEN = 0 V, VREFIN = 0,No Load 65 80μATA = 25 °C, VEN = 0 V, VREFIN > 0.4 V, NoLoad 200 400ILDOIN Supply current of VLDOIN TA = 25 °C, VEN = 3.3 V, No Load 1 50 μAILDOIN(SDN) Shutdown current of VLDOIN TA = 25 °C, VEN = 0 V, No Load 0.1 50 μAINPUT CURRENTIREFIN Input current, REFIN VEN = 3.3 V 1 μAVO OUTPUTVVOSNS Output DC voltage, VOVREFOUT = 1.25 V (DDR1), IO = 0 A1.25 V–15 15 mVVREFOUT = 0.9 V (DDR2), IO = 0 A0.9 V–15 15 mVVREFOUT = 0.75 V (DDR3), IO = 0 A0.75 V–15 15 mVVREFOUT = 0.675 V (DDR3L), IO = 0 A0.675 V–15 15 mVVREFOUT = 0.6 V (DDR4), IO = 0 A0.6 V–15 15 mVVVOTOL Output voltage tolerance to REFOUT –2 A < IVO < 2 A –25 25 mVIVOSRCL VO source current Limit With reference to REFOUT,VOSNS = 90% × VREFOUT3 4.5 AIVOSNCL VO sink current Limit With reference to REFOUT,VOSNS = 110% × VREFOUT3.5 5.5 AIDSCHRG Discharge current, VO VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA= 25°C18 25 ΩPOWERGOOD COMPARATORVTH(PG) VO PGOOD thresholdPGOOD window lower threshold withrespect to REFOUT –23.5% –20% –17.5%PGOOD window upper threshold withrespect to REFOUT 17.5% 20% 23.5%PGOOD hysteresis 5%tPGSTUPDLY PGOOD start-up delay Start-up rising edge, VOSNS within 15%of REFOUT 2 msVPGOODLOW Output low voltage ISINK = 4 mA 0.4 VtPBADDLY PGOOD bad delay VOSNS is outside of the ±20% PGOODwindow 10 μsIPGOODLK Leakage current(1) VOSNS = VREFIN (PGOOD highimpedance), VPGOOD = VVIN + 0.2 V1 μAREFIN AND REFOUTVREFIN REFIN voltage range 0.5 1.8 VVREFINUVLO REFIN undervoltage lockout REFIN rising 360 390 420 mVVREFINUVHYSREFIN undervoltage lockouthysteresis 20 mVVREFOUT REFOUT voltage REFIN V6TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments IncorporatedElectrical Characteristics (continued)Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT= 3 × 10 μF and circuit shown in Figure 24. (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITVREFOUTTOL REFOUT voltage tolerance to VREFIN–1 mA < IREFOUT < 1 mA,VREFIN = 1.25 V–12 12mV–1 mA < IREFOUT < 1 mA,VREFIN = 0.9 V–12 12–1 mA < IREFOUT < 1 mA,VREFIN = 0.75 V–12 12–1 mA < IREFOUT < 1 mA,VREFIN = 0.675 V–12 12–1 mA < IREFOUT < 1 mA,VREFIN = 0.6 V–12 12IREFOUTSRCL REFOUT source current limit VREFOUT = 0 V 10 40 mAIREFOUTSNCL REFOUT sink current limit VREFOUT = 0 V 10 40 mAUVLO AND EN LOGIC THRESHOLDVVINUVVIN UVLO thresholdWake up, TA = 25°C 2.2 2.3 2.375 VHysteresis 50 mVVENIH High-level input voltage Enable 1.7VENIL Low-level input voltage Enable 0.3 VVENYST Hysteresis voltage Enable 0.5IENLEAK Logic input leakage current EN, TA = 25°C –1 1 μATHERMAL SHUTDOWNTSON Thermal shutdown threshold(1) Shutdown temperature 150°CHysteresis 25±3 ±2 ±1 0 1Output Current (A)550570590610630650670Output Voltage (mV)2 30°C25°C85°C± 40°CTA±3 ±2 ±1 0 1Output Current (A)0.90.951.051.11.21.251.3Output Voltage (V)2 31.1510°C25°C85°C± 40°CTA±3 ±2 ±1 0 1Output Current (A)700710730740760780790Output Voltage (mV)2 30°C25°C85°C± 40°CTA770750720Output Current (A)±3 ±2 ±1 0 1 2640650660670680690700710720Output Voltage (mV)3TA±40°C0°C25°C85°C±3 ±2 ±1 0 1Output Current (A)1.181.21.221.241.261.281.3Output Voltage (V)2 30°C25°C85°C± 40°CTA±3 ±2 ±1 0 1Output Current (A)880890900910920930940Output Voltage (mV)2 30°C25°C85°C± 40°CTA8707TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated6.6 Typical Characteristics3 × 10-µF MLCCs (0805) are used on the outputVVIN = 3.3 V DDRFigure 1. Load RegulationVVIN = 3.3 V DDR2Figure 2. Load RegulationVVIN = 3.3 V DDR3Figure 3. Load RegulationVVIN = 3.3 V DDR3LFigure 4. Load RegulationVVIN = 3.3 V LP DDR3 or DDR4Figure 5. Load RegulationVVIN = 2.5 V DDRFigure 6. Load Regulation±15 ±10 ±5 0 5REFOUT Output Current (mA)1.2471.2491.251.2521.2541.255Output Voltage (V)10 151.2481.2511.25325°C85°C± 40°CTA±15 ±10 ±5 0 5REFOUT Output Current (mA)897899900902904905Output Voltage (mV)10 1589890190325°C85°C± 40°CTA±3 ±2 ±1 0 1Output Current (A)500550600650700750Output Voltage (mV)2 30°C25°C85°C± 40°CTAOutput Current (A)±3 ±2 ±1 0 1 2620630640650660670680690700710720TA±40°C0°C25°C85°C3Output Voltage (mV)±3 ±2 ±1 0 1Output Current (A)0.80.750.80.850.951Output Voltage (V)2 30.90°C25°C85°C± 40°CTA±3 ±2 ±1 0 1Output Current (A)650675700725825800Output Voltage (mV)2 37500°C25°C85°C± 40°CTA8TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments IncorporatedTypical Characteristics (continued)3 × 10-µF MLCCs (0805) are used on the outputVVIN = 2.5 V DDR2Figure 7. Load RegulationVVIN = 2.5 V DDR3Figure 8. Load RegulationVVIN = 2.5 V DDR3LFigure 9. Load RegulationVVIN = 2.5 V LP DDR3 or DDR4Figure 10. Load RegulationDDRFigure 11. REFOUT Load RegulationDDR2Figure 12. REFOUT Load Regulation60503020100±10±20±301 k 100 k 10 MFrequency (Hz)Gain (dB)Phase (°)10 k 1 MGainPhase200150100500±50±100±150±2004060503020100±10±20±301 k 100 k 10 MFrequency (Hz)Phase (°)Gain (dB)10 k 1 MGainPhase200150100500±50±100±150±20040±15 ±10 ±5 0 5REFOUT Output Current (mA)597599600602604605Output Voltage (mV)10 1559860160325°C85°C± 40°CTA0 0.5 1 2 2.5Output Current (A)00.40.61.21.4DROPOUT Voltage (V)3 3.50.20.811.50.750.91.25VOUT (V)0.6750.6±15 ±10 ±5 0 5REFOUT Output Current (mA)747749750752754755Output Voltage (mV)10 1525°C85°C± 40°CTA748751753REFOUT Output Current (mA)-15 -10 -5 0 5 10672673674675676677678679680Output Voltage (mV)TA±40°C25°C85°C159TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments IncorporatedTypical Characteristics (continued)3 × 10-µF MLCCs (0805) are used on the outputDDR3Figure 13. REFOUT Load RegulationDDR3LFigure 14. REFOUT Load RegulationLP DDR3 or DDR4Figure 15. REFOUT Load Regulation Figure 16. DROPOUT Voltage vs. Output CurrentDDR2Figure 17. Bode PlotDDR3Figure 18. Bode Plot++REFIN 1VIN 10EN 7VOSNS 5GND 82.3 VREFINOKENVTT2 VLDOIN6 REFOUT4 PGND3 VO9 PGOOD+++++Start-upDelayDchgREFDchgVTTUVLOGmGmCopyright © 2016, Texas Instruments Incorporated10TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated7 Detailed Description7.1 OverviewThe TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed forlow input voltage, low-cost, low-noise systems where space is a key consideration.The device maintains a fast transient response and only requires a minimum output capacitance of 20 μF. Thedevice supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, LowPower DDR3, and DDR4 VTT bus termination.7.2 Functional Block Diagram7.3 Feature Description7.3.1 Sink and Source Regulator (VO Pin)The TPS51200 is a sink and source tracking termination regulator specifically designed for low input voltage,low-cost, and low external component count systems where space is a key application parameter. The deviceintegrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinkingcurrent. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used tosupport the fast load transient response. To achieve tight regulation with minimum effect of trace resistance,connect a remote sensing terminal, VOSNS, to the positive terminal of each output capacitor as a separate tracefrom the high current path from VO.7.3.2 Reference Input (REFIN Pin)The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR terminationapplications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supplybus (VDDQ). The TPS51200 device supports REFIN voltages from 0.5 V to 1.8 V, making it versatile and idealfor many types of low-power LDO applications.11TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments IncorporatedFeature Description (continued)7.3.3 Reference Output (REFOUT Pin)When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage forthe memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUTbecomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT isless than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-kΩ MOSFET.REFOUT is independent of the EN pin state.7.3.4 Soft-Start SequencingA current clamp implements the soft-start function of the VO pin. The current clamp allows the output capacitorsto be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO isoutside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL) level.When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. Thesoft-start function is completely symmetrical and the overcurrent limit works for both directions. The soft-startfunction works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage.7.3.5 Enable Control (EN Pin)When EN is driven high, the VO regulator begins normal operation. When the device drives EN low, VOdischarges to GND through an internal 18-Ω MOSFET. REFOUT remains on when the device drives EN low.Ensure that the EN pin voltage remains lower than or equal to VVIN at all times.7.3.6 Powergood Function (PGOOD Pin)The TPS51200 device provides an open-drain PGOOD output that goes high when the VO output is within ±20%of REFOUT. PGOOD de-asserts within 10 μs after the output exceeds the size of the powergood window. Duringinitial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD isan open-drain output, a pull-up resistor with a value between 1 kΩ and 100 kΩ, placed between PGOOD and astable active supply voltage rail is required.7.3.7 Current Protection (VO Pin)The LDO has a constant overcurrent limit (OCL). The OCL level reduces by one-half when the output voltage isnot within the powergood window. This reduction is a non-latch protection.7.3.8 UVLO Protection (VIN Pin)For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage islower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown isa non-latch protection.7.3.9 Thermal ShutdownThe TPS51200 monitors junction temperature. If the device junction temperature exceeds the threshold value,(typically 150°C), the VO and REFOUT regulators both shut off, discharged by the internal discharge MOSFETs.This shutdown is a non-latch protection.7.3.10 Tracking Start-up and ShutdownThe TPS51200 also supports tracking start-up and shutdown when the EN pin is tied directly to the system busand not used to turn on or turn off the device. During tracking start-up, VO follows REFOUT once REFIN voltageis greater than 0.39 V. REFIN follows the rise of VDDQ rail through a voltage divider. The typical soft-start time(tSS) for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. Thesoft-start time of the VO output no longer depends on the OCL setting, but it is a function of the soft-start time ofthe VDDQ rail. PGOOD is asserted 2 ms after VVO is within ±20% of REFOUT. During tracking shutdown, the VOpin voltage falls following REFOUT until REFOUT reaches 0.37 V. When REFOUT falls below 0.37 V, theinternal discharge MOSFETs turn on and quickly discharge both REFOUT and VO to GND. PGOOD isdeasserted when VO is beyond the ±20% range of REFOUT. Figure 20 shows the typical timing diagram for anapplication that uses tracking start-up and shutdown.PGOODtSS determinedby the SS timeof VLDOIN2 msVOVVO = 0.75 VREFOUT(VTTREF)REFINVLDOIN3.3VINENPGOOD2 msVOREFINREFOUT(VTTREF)VLDOINVVDDQ = 1.5 V3.3VINEN(S3_SLP)tSS .VVO = 0.75 VtSS =COUT x VOIOOCL12TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments IncorporatedFeature Description (continued)Figure 19. Typical Timing Diagram for S3 and Pseudo-S5 SupportFigure 20. Typical Timing Diagram of Tracking Start-up and ShutdownRS20 WVOUT VIN25 WVTT VDDQOuputBuffer(Driver)ReceiverVSSUDG-08023Q1Q2DDR3 240 Pin SocketTPS5120010 mF 10 mF 10 mFVOSPDDQVttVddVttVddCACADQVddUDG-0802213TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments IncorporatedFeature Description (continued)7.3.11 Output Tolerance Consideration for VTT DIMM ApplicationsThe TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 21). TheDDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sinkand source current while maintaining acceptable VTT tolerance. See Figure 22 for typical characteristics for asingle memory cell.Figure 21. Typical Application Diagram for DDR3 VTT DIMM using TPS51200Figure 22. DDR Physical Signal System Bi-Directional SSTL SignalingIn Figure 22, when Q1 is on and Q2 is off:• Current flows from VDDQ via the termination resistor to VTT• VTT sinks currentIn Figure 22, when Q2 is on and Q1 is off:• Current flows from VTT via the termination resistor to GND• VTT sources currentMUGBWOUTgƒ2 C=´ p ´14TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments IncorporatedFeature Description (continued)Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand thetolerance requirement on VTT. Equation 1 applies to both DC and AC conditions and is based on JEDEC VTTspecifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).VVTTREF – 40 mV < VVTT < VVTTREF + 40 mV (1)The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.The TPS51200 ensures the regulator output voltage to be as shown in Equation 2, which applies to both DC andAC conditions.VVTTREF –25 mV < VVTT < VVTTREF + 25 mVwhere• –2 A < IVTT < 2 A (2)The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable toDDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 applications (see Table 1 for detailed information).To meet the stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actualtolerance on the MLCC capacitors, three 10-μF ceramic capacitors sufficiently meet the VTT accuracyrequirement.Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination TechnologyDDR DDR2 DR3 LOW POWER DDR3FSB DataRates 200, 266, 333, and 400 MHz 400, 533, 677, and 800 MHz 800, 1066, 1330, and 1600 MHzTermination Motherboard termination toVTT for all signalsOn-die termination for datagroup. VTT termination foraddress, command andcontrol signalsOn-die termination for data group. VTT termination foraddress, command and control signalsTerminationCurrentDemandMaximum source/sinktransient currents of up to 2.6A to 2.9 ANot as demanding Not as demandingOnly 34 signals (address,command, control) tied toVTTOnly 34 signals (address, command, control) tied to VTTODT handles data signals ODT handles data signalsLess than 1-A of burstcurrent Less than 1-A of burst currentVoltage Level 2.5-V Core andI/O 1.25-V VTT1.8-V Core andI/O 0.9-V VTT1.5-V Core andI/O 0.75-V VTT1.2-V Core andI/O 0.6-V VTTThe TPS51200 uses transconductance (gM) to drive the LDO. The transconductance and output current of thedevice determine the voltage droop between the reference input and the output regulator. The typicaltransconductance level is 250 S at 2 A and changes with respect to the load in order to conserve the quiescentcurrent (that is, the transconductance is very low at no load condition). The (gM) LDO regulator is a single polesystem. Only the output capacitance determines the unity gain bandwidth for the voltage loop, as a result of thebandwidth nature of the transconductance (see Equation 3).where• ƒUGBW is the unity gain bandwidth• gM is transconductance• COUT is the output capacitance (3)Consider these two limitations to this type of regulator that come from the output bulk capacitor requirement. Inorder to maintain stability, the zero location contributed by the ESR of the output capacitors must be greater thanthe –3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in thedesign. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order toprevent the gain peaking effect around the transconductance (gM) –3-dB point because of the large ESL, theoutput capacitor and parasitic inductance of the VO pin voltage trace.RREF Q2 × øVREFIREFVREFRREFRREFVVDDQDDR15TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated7.3.12 REFOUT (VREF) Consideration for DDR2 ApplicationsDuring TPS51200 tracking start-up, the REFIN voltage follows the rise of the VDDQ rail through a voltagedivider, and REFOUT (VREF) follows REFIN once the REFIN voltage is greater than 0.39 V. When the REFINvoltage is lower than 0.39 V, VREF is 0 V.The JEDEC DDR2 SDRAM Standard (JESD79-2E) states that VREF must track VDDQ/2 within ±0.3 V accuracyduring the start-up period. To allow the TPS51200device to meet the JEDEC DDR2 specification, a resistor divider can be used to provide the VREF signal to theDIMM. The resistor divider ratio is 0.5 to ensure that the VREF voltage equals VDDQ/2.Figure 23. Resistor Divider CircuitWhen selecting the resistor value, consider the impact of the leakage current from the DIMM VREF pin on thereference voltage. Use Equation 4 to calculate resistor values.where• RREF is the resistor value• ∆VREF is the VREF DC variation requirement• IREF is the maximum total VREF leakage current from DIMMs (4)Consider the MT47H64M16 DDR2 SDRAM component from Micron as an example. The MT47H64M16datasheet shows the maximum VREF leakage current of each DIMM is ±2 µA, and VREF(DC) variation must bewithin ±1% of VDDQ. In this DDR2 application, the VDDQ voltage is 1.8 V. Assuming one TPS51200 deviceneeds to power 4 DIMMs, the maximum total VREF leakage current is ±8 µA. Based on the calculations, theresistor value should be lower than 4.5 kΩ. To ensure sufficient margin, 100 Ω is the suggested resistor value.With two 100-Ω resistors, the maximum VREF variation is 0.4 mV, and the power loss on each resistor is 8.1 mW.16TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated7.4 Device Functional Modes7.4.1 Low Input Voltage ApplicationsTPS51200 can be used in an application system that offers either a 2.5-V rail or a 3.3-V rail. If only a 5-V rail isavailable, consider using the TPS51100 device as an alternative. The TPS51200 device has a minimum inputvoltage requirement of 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC andtransient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between –5%and 5% accuracy, or better.7.4.2 S3 and Pseudo-S5 SupportThe TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal inthe end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VOis turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low andthe REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs areturned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4 or S5state). Figure 19 shows a typical start-up and shutdown timing diagram for an application that uses S3 andpseudo-S5 support.23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 kW3.3 VINPGOODSLP_S3C50.1 mFVTTREFVVLDOIN = VVDDQ = 1.5 VVVTT = 0.75 VC41000 pFR110 kWVVDDQ = 1.5 VR210 kWUDG-08029C64.7 mFC810 mFC710 mFC310 mFC210 mFC110 mF17TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated8 Application and ImplementationNOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.8.1 Application Information8.2 Typical ApplicationThis design example describes a 3.3-VIN, DDR3 configuration.Figure 24. 3.3-VIN, DDR3 ConfigurationTable 2. 3.3-VIN, DDR3 Application List of MaterialsREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1, R2Resistor10 kΩR3 100 kΩC1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata18TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated8.2.1 Design Requirements• VIN = 3.3 V• VDDDQ = 1.5 V• VVLDOIN = VVDDQ = 1.5 V• VVTT = 0.75 V8.2.2 Detailed Design Procedure8.2.2.1 Input Voltage CapacitorAdd a ceramic capacitor, with a value between 1.0-μF and 4.7-μF, placed close to the VIN pin, to stabilize thebias supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply.8.2.2.2 VLDO Input CapacitorDepending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase ofsource current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or greater)ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance isused at the VO pin. In general, use one-half of the COUT value for input.8.2.2.3 Output CapacitorFor stable operation, the total capacitance of the VO output pin must be greater than 20 μF. Attach three, 10-μFceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent seriesinductance (ESL). If the ESR is greater than 2 mΩ, insert an RC filter between the output and the VOSNS inputto achieve loop stability. The RC filter time constant should be almost the same as or slightly lower than the timeconstant of the output capacitor and its ESR.±3 ±2 ±1 0 1Output Current (A)700710730740760780790Output Voltage (mV)2 30°C25°C85°C± 40°CTA77075072080400±40±801 M 100 MFrequency (Hz)Phase (°)100 k 10 M±360±2700GainPhase±180±90Gain (dB)1 10 1000 100 10 k19TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated8.2.3 Application CurvesFigure 25 shows the bode plot simulation for this DDR3 design example of the TPS51200 device.The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, thegain peaks because of the ESL effect. However, the peaking maintains a level well below 0 dB.Figure 26 shows the load regulation and Figure 27 shows the transient response for a typical DDR3configuration. When the regulator is subjected to ±1.5-A load step and release, the output voltage measurementshows no difference between the dc and ac conditions.VIN = 3.3 V VVLDOIN = 1.5 V VVO = 0.75 VIIO = 2 A 3 × 10-μF capacitors ESR = 2.5 mΩESL = 800 pHFigure 25. DDR3 Design Example Bode PlotVVIN = 3.3 V DDR3Figure 26. Load Regulation Figure 27. Transient Waveform23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 k:3.3 VINPGOODSLP_S3C50.1 PFVTTREFVVLDOIN = VVDDQ = 1.8 VVVTT = 0.9 VC41000 pFR110 k:VVDDQ = 1.8 VR210 k:C64.7 PFC810 PFC710 PFC310 PFC210 PFC110 PFR5100 üVVDDQ = 1.8 VR4100 ü20TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated8.3 System Examples8.3.1 3.3-VIN, DDR2 ConfigurationThis section describes a 3.3-VIN, DDR2 configuration application.Figure 28. 3.3-VIN, DDR2 ConfigurationTable 3. 3.3-VIN, DDR2 Configuration List of MaterialsREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1, R2Resistor10 kΩR3 100 kΩR4, R5 100 ΩC1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 kW2.5 VINPGOODSLP_S3C50.1 mFVTTREFVVLDOIN = VVDDQ = 1.5 VVVTT = 0.75 VC41000 pFR110 kWVVDDQ = 1.5 VR210 kWUDG-08030C64.7 mFC810 mFC710 mFC310 mFC210 mFC110 mF21TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated8.3.2 2.5-VIN, DDR3 ConfigurationThis design example describes a 2.5-VIN, DDR3 configuration application.Figure 29. 2.5-VIN, DDR3 ConfigurationTable 4. 2.5-VIN, DDR3 Configuration List of MaterialsREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1, R2Resistor10 kΩR3 100 kΩC1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 kW3.3 VINPGOODSLP_S3C50.1 mFVTTREFVVLDOIN = VVDDQ = 1.2 VVVTT = 0.6 VC41000 pFR110 kWVVDDQ = 1.2 VR210 kWUDG-08031C64.7 mFC810 mFC710 mFC310 mFC210 mFC110 mF22TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated8.3.3 3.3-VIN, LP DDR3 or DDR4 ConfigurationThis example describes a 3.3-VIN, LP DDR3 or DDR4 configuration application.Figure 30. 3.3-VIN, LP DDR3 or DDR4 ConfigurationTable 5. 3.3-VIN, LP DDR3 or DDR4 ConfigurationREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1, R2Resistor10 kΩR3 100 kΩC1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 kW3.3 VINPGOODC50.1 mFVTTREFVVLDOIN = VVDDQ = 1.5 VVVTT = 0.75 VC41000 pFR110 kWVVDDQ = 1.5 VR210 kWUDG-08032C64.7 mFC810 mFC710 mFC310 mFC210 mFC110 mF23TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated8.3.4 3.3-VIN, DDR3 Tracking ConfigurationThis design example describes a 3.3-VIN, DDR3 tracking configuration application.Figure 31. 3.3-VIN, DDR3 Tracking ConfigurationTable 6. 3.3-VIN, DDR3 Tracking Configuration List of MaterialsREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1, R2Resistor10 kΩR3 100 kΩC1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 k:3.3 VINPGOODENABLEC50.1 PFREFOUTVVLDOIN = VVLDOREF = 2.5 VVVLDO = 1.8 VC41000 pFR13.86 k:2.5 VR210 k:UDG-08033C64.7 PFC810 PFC710 PFC310 PFC210 PFC110 PF24TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated8.3.5 3.3-VIN, LDO ConfigurationThis example describes a 3.3-VIN, LDO configuration application.Figure 32. 3.3-VIN, LDO ConfigurationTable 7. 3.3-VIN, LDO Configuration List of MaterialsREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1Resistor3.86 kΩR2 10 kΩR3 100 kΩC1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L Murata23451987610TPS51200REFINVLDOINVOPGNDVOSNSVINPGOODGNDENREFOUTR3100 kW3.3 VINPGOODSLP_S3C50.1 mFVTTREFVVLDOIN = VVDDQ = 1.5 VVVTT = 0.75 VC41000 pFR110 kWVVDDQ = 1.5 VR210 kWUDG-08034C64.7 mFC810 mFC710 mFC310 mFC210 mFC110 mFR4(1)C9(1) 25TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated(1) Choose values for R4 and C9 to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output capacitors(ESR and ESL).8.3.6 3.3-VIN, DDR3 Configuration with LFPThis design example describes a 3.3-VIN, DDR3 configuration with LFP application.Figure 33. 3.3-VIN, DDR3 Configuration with LFPTable 8. 3.3-VIN, DDR3 Configuration with LFP List of MaterialsREFERENCEDESIGNATOR DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERR1, R2Resistor10 kΩR3 100 kΩR4(1)C1, C2, C3Capacitor10 μF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 μFC6 4.7 μF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 μF, 6.3 V GRM21BR70J106KE76L MurataC9(1)26TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cnCopyright © 2008–2020, Texas Instruments Incorporated9 Power Supply RecommendationsThis device is designed to operate from an input bias voltage from 2.375 V to 3.5 V, with LDO input from 1.1 V to3.5 V. Refer to Figure 19 and Figure 20 for recommended power-up sequence. Maintain a EN voltage equal orlower than VVIN at all times. VLDOIN can ramp up earlier than VIN if the sequence in Figure 19 and Figure 20cannot be used. The input supplies should be well regulated. VLDOIN decoupling capacitanceof 2 × 10 µF is recommended, and VIN decoupling capacitance of 1 × 4.7 µF is recommended.10 Layout10.1 Layout GuidelinesConsider the following points before starting the TPS51200 device layout design.• Place the input capacitors as close to VDLOIN pin as possible with short and wide connection.• Place the output capacitor as close to VO pin as possible with short and wide connection. Place a ceramiccapacitor with a value of at least 10-µF as close to VO pin if the rest of output capacitors need to be placedon the load side.• Connect the VOSNS pin to the positive node of output capacitors as a separate trace. In DDR VTTapplication, connect the VO sense trace to DIMM side to ensure the VTT voltage at DIMM side is wellregulated.• Consider adding low-pass filter at VOSNS if the VO sense trace is very long.• Connect the GND pin and PGND pin to the thermal pad directly.• TPS51200 uses its thermal pad to dissipate heat. In order to effectively remove heat fromTPS51200 package,place numerous ground vias on the thermal pad. Use large ground copper plane, especially the copper planeon surface layer, to pour over those vias on thermal pad.• Consult the TPS51200EVM User's Guide (SLUU323) for detailed layout recommendations.P V I D _ SNK VO SNK = ´ P (V V ) I D _ SRC VLDOIN VO O _ SRC = - ´ToGNDPlaneGNDVLDOINEN TraceVIN TraceVTTPGOOD TraceVDDQ TraceVTT Sense Trace,terminate near the load27TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020Copyright © 2008–2020, Texas Instruments Incorporated10.2 Layout ExampleFigure 34. Layout Recommendation10.3 Thermal Design ConsiderationsBecause the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, therebydissipating power from the device. When the device is sourcing current, the voltage difference shown inEquation 5 calculates the power dissipation.(5)In this case, if the VLDOIN pin is connected to an alternative power supply lower than the VDDQ voltage, overallpower loss can be reduced. During the sink phase, the device applies the VO voltage across the internal LDOregulator. Equation 6 calculates he power dissipation, PD_SNK can be calculated by .(6)Because the device does not sink and source current at the same time and the I/O current may vary rapidly withtime, the actual power dissipation should be the time average of the above dissipations over the thermalrelaxation duration of the system. The current used for the internal current control circuitry from the VIN supplyand the VLDOIN supply are other sources of power consumption. This power can be estimated as 5 mW or lessduring normal operating conditions and must be effectively dissipated from the package. 1 mmTT on top of packageTB on PCB surfaceLand Pad3 mm x 1.9 mmExposed ThermalDie Pad,2.48 mm x 1.74 mmUDG-08018 T T P J B JB D = + Y ´ T T P J T JT D = + Y ´J(max) A(max)PKGJAT TP-=q28TPS51200ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020 www.ti.com.cn版权 © 2008–2020, Texas Instruments IncorporatedThermal Design Considerations (continued)Maximum power dissipation allowed by the package is calculated by Equation 7.where• TJ(max) is 125°C• TA(max) is the maximum ambient temperature in the system• θJA is the thermal resistance from junction to ambient (7)NOTEBecause Equation 7 demonstrates the effects of heat spreading in the ground plane, use itas a guideline only. Do not use Equation 7 to estimate actual thermal performance in realapplication environments.In an application where the device is mounted on PCB, TI strongly recommends using ψJT and ψJB, as explainedin the section pertaining to estimating junction temperature in the Semiconductor and IC Package ThermalMetrics application report, SPRA953. Using the thermal metrics ψJT and ψJB, as shown in the ThermalInformation table, estimate the junction temperature with corresponding formulas shown in Equation 8. The olderθJC top parameter specification is listed as well for the convenience of backward compatibility.(8)where• PD is the power dissipation shown in Equation 5 and Equation 6• TT is the temperature at the center-top of the IC package• TB is the PCB temperature measured 1-mm away from the thermal pad package on the PCB surface (seeFigure 36). (9)NOTEBoth TT and TB can be measured on actual application boards using a thermo-gun (aninfrared thermometer). For more information about measuring TT and TB, see theapplication report Using New Thermal Metrics (SBVA025)..Figure 35. Recommended Land Pad Pattern Figure 36. Package Thermal Measurement29TPS51200www.ti.com.cn ZHCSL06D –FEBRUARY 2008–REVISED FEBRUARY 2020版权 © 2008–2020, Texas Instruments Incorporated11 器件和文档支持11.1 器件支持11.1.1 第三方产品免责声明TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。11.1.2 开发支持11.1.2.1 评估模块我们为您提供了评估模块 (EVM)，可帮助对使用 TPS51200 器件的电路进行初始性能评估。TPS51200EVM 评估模块以及相关的用户指南 (SLUU323) 可在德州仪器 (TI) 网站上的产品文件夹中获取，也可直接从 TI 网上商店购买。11.1.2.2 Spice 模型分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。单击此处可获取TPS51200 器件的 SPICE 模型。11.2 文档支持11.2.1 相关文档• 《使用新的热指标》，SBVA025• 《半导体和 IC 封装热指标》，SPRA953• 《使用 TPS51200 EVM 灌电流/拉电流 DDR 终端稳压器》，SLUU323• 有关 TPS51100 器件的更多信息，请参见 ti.com 上的产品文件夹。11.3 社区资源TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and donot necessarily reflect TI's views; see TI's Terms of Use.11.4 商标E2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.11.5 静电放电警告这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。11.6 GlossarySLYZ022 — TI Glossary.This glossary lists and explains terms, acronyms, and definitions.12 机械、封装和可订购信息以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。重要声明和免责声明TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保。所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122Copyright © 2020 德州仪器半导体技术（上海）有限公司PACKAGE OPTION ADDENDUMwww.ti.com 10-Dec-2020Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEco Plan(2)Lead finish/Ball material(6)MSL Peak Temp(3)Op Temp (°C) Device Marking(4/5)SamplesTPS51200DRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 1200TPS51200DRCRG4 ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 1200TPS51200DRCT ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 1200TPS51200DRCTG4 ACTIVE VSON DRC 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 1200(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as &quotb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andPACKAGE OPTION ADDENDUMwww.ti.com 10-Dec-2020Addendum-Page 2continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantTPS51200DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2TPS51200DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2PACKAGE MATERIALS INFORMATIONwww.ti.com 23-Mar-2020Pack Materials-Page 1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)TPS51200DRCR VSON DRC 10 3000 367.0 367.0 35.0TPS51200DRCT VSON DRC 10 250 210.0 185.0 35.0PACKAGE MATERIALS INFORMATIONwww.ti.com 23-Mar-2020Pack Materials-Page 2www.ti.comGENERIC PACKAGE VIEWThis image is a representation of the package family, actual package may vary.Refer to the product data sheet for package details.DRC 10 VSON - 1 mm max height3 x 3, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD4226193/Awww.ti.comPACKAGE OUTLINEC10X 0.300.182.4 0.12X21.65 0.18X 0.51.00.810X 0.50.30.050.00A 3.12.9B3.12.9(0.2) TYP 4X (0.25)2X (0.5)DRC0010J VSON - 1 mm max heightPLASTIC SMALL OUTLINE - NO LEAD4218878/B 07/2018PIN 1 INDEX AREASEATING PLANE0.08 C15 610(OPTIONAL)PIN 1 ID 0.1 C A B0.05 CTHERMAL PADEXPOSEDSYMM11 SYMMNOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancingper ASME Y14.5M.2. This drawing is subject to change without notice.3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.SCALE 4.000www.ti.comEXAMPLE BOARD LAYOUT0.07 MIN0.07 MAX ALL AROUNDALL AROUND10X (0.24)(2.4)(2.8)8X (0.5)(1.65)( 0.2) VIATYP(0.575)(0.95)10X (0.6)(R0.05) TYP(3.4)(0.25)(0.5)DRC0010J VSON - 1 mm max heightPLASTIC SMALL OUTLINE - NO LEAD4218878/B 07/2018SYMM15 610LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:20X11SYMMNOTES: (continued)4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literaturenumber SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.SOLDER MASKSOLDER MASK OPENINGMETAL UNDERSOLDER MASKDEFINEDEXPOSED METALSOLDER MASK METALOPENINGSOLDER MASK DETAILSNON SOLDER MASKDEFINED(PREFERRED)EXPOSED METALwww.ti.comEXAMPLE STENCIL DESIGN(R0.05) TYP10X (0.24)10X (0.6)2X (1.5)2X(1.06)(2.8)(0.63)8X (0.5)(0.5)4X (0.34)4X (0.25)(1.53)DRC0010J VSON - 1 mm max heightPLASTIC SMALL OUTLINE - NO LEAD4218878/B 07/2018NOTES: (continued)6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILEXPOSED PAD 11:80% PRINTED SOLDER COVERAGE BY AREASCALE:25XSYMM15 610EXPOSED METAL11 TYPSYMM重要声明和免责声明TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保。所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122Copyright © 2020 德州仪器半导体技术（上海）有限公

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