黑金AX4010 FPGA开发板流水灯例程 EP4CE10F17C8

1. `timescale 1ns / 1ps
2. module LED
3. (
4.     input           clk,           // system clock 50Mhz on board
5.     input           rst_n,         // reset ,low active
6.     output reg[3:0] led            // LED,use for control the LED signal on board
7. );
9. //define the time counter
10. reg [31:0]      timer;
12. // cycle counter:from 0 to 4 sec
13. always@(posedge clk or negedge rst_n)
14. begin
15.     if (rst_n == 1'b0)
16.         timer <= 32'd0;                     //when the reset signal valid,time counter clearing
17.     else if (timer == 32'd199_999_999)      //4 seconds count(50M*4-1=199999999)
18.         timer <= 32'd0;                     //count done,clearing the time counter
19.     else
20.         timer <= timer + 32'd1;             //timer counter = timer counter + 1
21. end
22. // LED control
23. always@(posedge clk or negedge rst_n)
24. begin
25.     if (rst_n == 1'b0)
26.         led <= 4'b0000;                     //when the reset signal active
27.     else if (timer == 32'd49_999_999)       //time counter count to 1st sec,LED1 lighten
28.         led <= 4'b0001;
29.     else if (timer == 32'd99_999_999)       //time counter count to 2nd sec,LED2 lighten
30.         led <= 4'b0010;
31.     else if (timer == 32'd149_999_999)      //time counter count to 3rd sec,LED3 lighten
32.         led <= 4'b0100;
33.     else if (timer == 32'd199_999_999)      //time counter count to 4th sec,LED4 lighten
34.         led <= 4'b1000;
35. end
36. endmodule

复制代码

  

    

    

    

666666