DDR3__Layout_Design

lcgoneone · 发表于 2012-10-28 17:46:50

The design guidelines presented in this application note
apply to products that leverage the DDR3 SDRAM IP core,
and they are based on a compilation of internal platforms
designed by Freescale Semiconductor, Inc. The purpose of
these guidelines is to minimize board-related issues across
multiple memory topologies while allowing maximum
flexibility for the board designer.
Freescale highly recommends that the system/board designer
verify all design aspects (signal integrity, electrical timings,
and so on) through simulation before PCB fabrication.

DDR3__Layout_Design.pdf (512 KB, 下载次数: 1)