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fine CIF_CIF_FRM1_ADDR_Y 0x1c
#define CIF_CIF_FRM1_ADDR_UV 0x20
#define CIF_CIF_VIR_LINE_WIDTH 0x24
#define CIF_CIF_SET_SIZE 0x28
#define CIF_CIF_SCM_ADDR_Y 0x2c
#define CIF_CIF_SCM_ADDR_U 0x30
#define CIF_CIF_SCM_ADDR_V 0x34
#define CIF_CIF_WB_UP_FILTER 0x38
#define CIF_CIF_WB_LOW_FILTER 0x3c
#define CIF_CIF_WBC_CNT 0x40
#define CIF_CIF_CROP 0x44
#define CIF_CIF_SCL_CTRL 0x48
#define CIF_CIF_SCL_DST 0x4c
#define CIF_CIF_SCL_FCT 0x50
#define CIF_CIF_SCL_VALID_NUM 0x54
#define CIF_CIF_LINE_LOOP_CTR 0x58
#define CIF_CIF_FRAME_STATUS 0x60
#define CIF_CIF_CUR_DST 0x64
#define CIF_CIF_LAST_LINE 0x68
#define CIF_CIF_LAST_PIX 0x6c
/*The key register bit descrition*/
/* CIF_CTRL Reg , ignore SCM,WBC,ISP,*/
#define DISABLE_CAPTURE (0x00<<0)
#define ENABLE_CAPTURE (0x01<<0)
#define MODE_ONEFRAME (0x00<<1)
#define MODE_PINGPONG (0x01<<1)
#define MODE_LINELOOP (0x02<<1)
#define AXI_BURST_16 (0x0F << 12)
/*CIF_CIF_INTEN*/
#define FRAME_END_EN (0x01<<1)
#define BUS_ERR_EN (0x01<<6)
#define SCL_ERR_EN (0x01<<7)
/*CIF_CIF_FOR*/
#define VSY_HIGH_ACTIVE (0x01<<0)
#define VSY_LOW_ACTIVE (0x00<<0)
#define HSY_LOW_ACTIVE (0x01<<1)
#define HSY_HIGH_ACTIVE (0x00<<1)
#define INPUT_MODE_YUV (0x00<<2)
#define INPUT_MODE_PAL (0x02<<2)
#define INPUT_MODE_NTSC (0x03<<2)
#define INPUT_MODE_RAW (0x04<<2)
#define INPUT_MODE_JPEG (0x05<<2)
#define INPUT_MODE_MIPI (0x06<<2)
#define YUV_INPUT_ORDER_UYVY(ori) (ori & (~(0x03<<5)))
#define YUV_INPUT_ORDER_YVYU(ori) ((ori & (~(0x01<<6)))|(0x01<<5))
#define YUV_INPUT_ORDER_VYUY(ori) ((ori & (~(0x01<<5))) | (0x1<<6))
#define YUV_INPUT_ORDER_YUYV(ori) (ori|(0x03<<5))
#define YUV_INPUT_422 (0x00<<7)
#define YUV_INPUT_420 (0x01<<7)
#define INPUT_420_ORDER_EVEN (0x00<<8)
#define INPUT_420_ORDER_ODD (0x01<<8)
#define CCIR_INPUT_ORDER_ODD (0x00<<9)
#define CCIR_INPUT_ORDER_EVEN (0x01<<9)
#define RAW_DATA_WIDTH_8 (0x00<<11)
#define RAW_DATA_WIDTH_10 (0x01<<11)
#define RAW_DATA_WIDTH_12 (0x02<<11)
#define YUV_OUTPUT_422 (0x00<<16)
#define YUV_OUTPUT_420 (0x01<<16)
#define OUTPUT_420_ORDER_EVEN (0x00<<17)
#define OUTPUT_420_ORDER_ODD (0x01<<17)
#define RAWD_DATA_LITTLE_ENDIAN (0x00<<18)
#define RAWD_DATA_BIG_ENDIAN (0x01<<18)
#define UV_STORAGE_ORDER_UVUV (0x00<<19)
#define UV_STORAGE_ORDER_VUVU (0x01<<19)
/*CIF_CIF_SCL_CTRL*/
#define ENABLE_SCL_DOWN (0x01<<0)
#define DISABLE_SCL_DOWN (0x00<<0)
#define ENABLE_SCL_UP (0x01<<1)
#define DISABLE_SCL_UP (0x00<<1)
#define ENABLE_YUV_16BIT_BYPASS (0x01<<4)
#define DISABLE_YUV_16BIT_BYPASS (0x00<<4)
#define ENABLE_RAW_16BIT_BYPASS (0x01<<5)
#define DISABLE_RAW_16BIT_BYPASS (0x00<<5)
#define ENABLE_32BIT_BYPASS (0x01<<6)
#define DISABLE_32BIT_BYPASS (0x00<<6)
extern unsigned long rk_cif_grf_base;
extern unsigned long rk_cif_cru_base;
#define MIN(x,y) ((x<y) ? x: y)
#define MAX(x,y) ((x>y) ? x: y)
#define RK_SENSOR_24MHZ 24*1000*1000 /* MHz */
#define RK_SENSOR_48MHZ 48
#define __raw_readl(p) (*(unsigned int *)(p))
#define __raw_writel(v,p) (*(unsigned int *)(p) = (v))
#define write_cif_reg(base,addr, val) __raw_writel(val, addr+(base))
#define read_cif_reg(base,addr) __raw_readl(addr+(base))
#define mask_cif_reg(addr, msk, val) write_cif_reg(addr, (val)|((~(msk))&read_cif_reg(addr)))
static u32 CRU_PCLK_REG30;
static u32 CRU_CLK_OUT;
static u32 clk_cif_out_src_gate_en;
static u32 CRU_CLKSEL29_CON;
static u32 cif0_clk_sel;
static u32 ENANABLE_INVERT_PCLK_CIF0;
static u32 DISABLE_INVERT_PCLK_CIF0;
static u32 ENANABLE_INVERT_PCLK_CIF1;
static u32 DISABLE_INVERT_PCLK_CIF1;
static u32 CHIP_NAME;
#define write_cru_reg(addr, val) __raw_writel(val, addr+RK_CRU_VIRT)
#define read_cru_reg(addr) __raw_readl(addr+RK_CRU_VIRT)
#define mask_cru_reg(addr, msk, val) write_cru_reg(addr,(val)|((~(msk))&read_cru_reg(addr)))
#define rk3368_write_cru_reg(addr, val) __raw_writel(val, addr+rk_cif_cru_base)
#define rk3368_read_cru_reg(addr) __raw_readl(addr+rk_cif_cru_base)
#define rk3368_mask_cru_reg(addr, msk, val) rk3368_write_cru_reg(addr,(val)|((~(msk))&rk3368_read_cru_reg(addr)))
#define CAM_WORKQUEUE_IS_EN() (true)
#define CAM_IPPWORK_IS_EN() (false)/*((pcdev->zoominfo.a.c.width != pcdev->icd->user_width) || (pcdev->zoominfo.a.c.height != pcdev->icd->user_height))*/
#define IS_CIF0() (true)/*(pcdev->hostid == RK_CAM_PLATFORM_DEV_ID_0)*/
#if (CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_IPP)
#define CROP_ALIGN_BYTES (0x03)
#define CIF_DO_CROP 0
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_ARM)
#define CROP_ALIGN_BYTES (0x0f)
#define CIF_DO_CROP 0
#elif (CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_RGA)
#define CROP_ALIGN_BYTES (0x03)
#define CIF_DO_CROP 0
#elif(CONFIG_CAMERA_SCALE_CROP_MACHINE == RK_CAM_SCALE_CROP_PP)
#define CROP_ALIGN_BYTES (0x0F)
#define CIF_DO_CROP 1
#endif
/*
*v0.1.0 : this driver is 3.10 kernel driver;
copy and updata from v0.3.0x19;
support rk312x;
*v0.1.1:
1. spin lock in struct rk_cif_clk is not neccessary,and scheduled func clk_get called in this spin lock scope
cause warning, so remove this spin lock .
*v0.1.2:
1. rk3126 and rk3128 use different dts file.
*v0.1.3:
1. i2c 1 and wifi use the common io in rk3128,so just enable i2c1 in rk3126 dts file
*v0.1.4:
1. When cif was at work, the aclk is closed ,may cause bus abnormal ,so sleep 100ms before close aclk
*v0.1.5:
1. Improve the code to support all configuration.reset,af,flash...
*v0.1.6:
1. Delete SOCAM_DATAWIDTH_8 in SENSOR_BUS_PARAM parameters,it conflict with V4L2_MBUS_PCLK_SAMPLE_FALLING.
*v0.1.7:
1. Add power and powerdown controled by PMU.
*v0.1.8:
1. Support front and rear camera support are the same.
*v0.1.9:
1. Support pingpong mode.
2. Fix cif_clk_out cannot close which base on XIN24M and cannot turn to 0
3. Move Camera Sensor Macro from rk_camera.h to rk_camera_sensor_info.h
4. Support flash control when preview size == picture size
*v0.1.a:
1. Support rk3288 cif driver
2. Query and upload iommu info
*v0.1.b:
1. Vpu_service compatible has change ,fix it.
*v0.1.c:
1. setting cif capture en bit can't stop cif really,reset cif instead.
*v0.1.d:
1. use of_find_node_by_name to get vpu node instead of of_find_compatible_node
*v0.1.e:
1. support focus mode.
*v0.1.f:
1. focus mode have some bug,fix it.
*v0.2.0:
1. support rk3368.
*/
#define RK_CAM_VERSION_CODE KERNEL_VERSION(0, 2, 0)
static int version = RK_CAM_VERSION_CODE;
module_param(version, int, S_IRUGO);
/* limit to rk29 hardware capabilities */
#define RK_CAM_BUS_PARAM (V4L2_MBUS_MASTER |\
V4L2_MBUS_HSYNC_ACTIVE_HIGH |\
V4L2_MBUS_HSYNC_ACTIVE_LOW |\
V4L2_MBUS_VSYNC_ACTIVE_HIGH |\
V4L2_MBUS_VSYNC_ACTIVE_LOW |\
V4L2_MBUS_PCLK_SAMPLE_RISING |\
V4L2_MBUS_PCLK_SAMPLE_FALLING|\
V4L2_MBUS_DATA_ACTIVE_HIGH |\
V4L2_MBUS_DATA_ACTIVE_LOW|\
SOCAM_DATAWIDTH_8|SOCAM_DATAWIDTH_10|\
SOCAM_MCLK_24MHZ |SOCAM_MCLK_48MHZ)
#define RK_CAM_W_MIN 48
#define RK_CAM_H_MIN 32
#define RK_CAM_W_MAX 3856 /* ddl@rock-chips.com : 10M Pixel */
#define RK_CAM_H_MAX 2764
#define RK_CAM_FRAME_INVAL_INIT 0
#define RK_CAM_FRAME_INVAL_DC 0 /* ddl@rock-chips.com : */
#define RK30_CAM_FRAME_MEASURE 5
extern void videobuf_dma_contig_free(struct videobuf_queue *q, struct videobuf_buffer *buf);
extern dma_addr_t videobuf_to_dma_contig(struct videobuf_buffer *buf);
/* buffer for one video frame */
struct rk_camera_buffer
{
/* common v4l buffer stuff -- must be first */
struct videobuf_buffer vb;
enum v4l2_mbus_pixelcode code;
int inwork;
};
enum rk_camera_reg_state
{
Reg_Invalidate,
Reg_Validate
};
struct rk_camera_reg
{
unsigned int cifCtrl;
unsigned int cifCrop;
unsigned int cifFs;
unsigned int cifIntEn;
unsigned int cifFmt;
unsigned int cifVirWidth;
unsigned int cifScale;
/* unsigned int VipCrm;*/
enum rk_camera_reg_state Inval;
};
struct rk_camera_work
{
struct videobuf_buffer *vb;
struct rk_camera_dev *pcdev;
struct work_struct work;
struct list_head queue;
unsigned int index;
};
struct rk_camera_frmivalenum
{
struct v4l2_frmivalenum fival;
struct rk_camera_frmivalenum *nxt;
};
struct rk_camera_frmivalinfo
{
struct soc_camera_device *icd;
struct rk_camera_frmivalenum *fival_list;
};
struct rk_camera_zoominfo
{
struct semaphore sem;
struct v4l2_crop a;
int vir_width;
int vir_height;
int zoom_rate;
};
#if CAMERA_VIDEOBUF_ARM_ACCESS
struct rk29_camera_vbinfo
{
unsigned long phy_addr;
void __iomem *vir_addr;
unsigned int size;
};
#endif
struct rk_camera_timer{
struct rk_camera_dev *pcdev;
struct hrtimer timer;
bool istarted;
};
struct rk_cif_clk
{
/************must modify start************/
struct clk *pd_cif;
struct clk *aclk_cif;
struct clk *hclk_cif;
struct clk *cif_clk_in;
struct clk *cif_clk_out;
/************must modify end************/
// spinlock_t lock;
bool on;
};
struct rk_cif_crop
{
spinlock_t lock; |
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发表于 2016-10-26 16:46:01
