verilog 流水灯

suji10

reg [3:0]led=0;
reg [1:0]state=0;
reg [23:0]counter=0;
always@(posedge clk)
begin
counter<=counter+1'h1;
if(counter==10000)
state<=state+1'h1;
end
always@(posedge clk )
begin
case(state)
0: led<=4'b0001;
1: led<=4'b0010;
2: led<=4'b0100;
3: led<=4'b1000;
endcase
end

cdl511

谢谢分享

yoyole103