cpld与8051的总线接口vhdl设计源码 - FPGA/CPLD - 电子工程师俱

2dmin

8051工作频率为11.0592MHZCPLD(EPM7128SLC15)的工作频率为16.0000MHZ(有源晶振)
<ol><li> <li> <li>library IEEE;<li>use IEEE.std_logic_1164.all;<li>use IEEE.std_logic_unsigned.all;<li>entity cpldbus51 is<li> port (    <li>Clk: in STD_LOGIC;       --Clock  16MHZ<li>Clr: in STD_LOGIC;   --Clear high <li&gt0: inout STD_LOGIC_VECTOR (7 downto 0); --8052 Port 0<li&gt2: in STD_LOGIC_VECTOR (7 downto 0);  --8052 Port 2<li>ALE: in STD_LOGIC;         --8052 ALE<li>--PSEN: in STD_LOGIC;   --8052&#39sen<li>--INT0utSTD_LOGIC;       --8052 INT0<li>Wr: in STD_LOGIC;   --8052'Wr<li>Rd: in STD_LOGIC;   --8052'Rd<li>---------------------------<li&gtinaut STD_LOGIC;       ---output <li>-----------------------<li>nCS8255: out STD_LOGIC;   --select 8255<li>RamBank: out STD_LOGIC_VECTOR (1 downto 0);--Ram68128a bank switch A15 A16<li>nCsFlashRam: out STD_LOGIC;   --select Flash Rom CE<li>FlashRomBank: out STD_LOGIC_VECTOR (2 downto 0) --Flash Rom switchA14 A15 A16<li> <li> );<li>end cpldbus51;<li> <li>architecture cpldbus51 of cpldbus51 is   <li>------------------------------------------------------------------------------<li>signal Addr: std_logic_vector(15 downto 0);--16bit address<li>signal ALE_Sample:STD_LOGIC;<li>signal RamBankReg: STD_LOGIC_VECTOR (1 downto 0);--Ram bank switch reg, 4 banks, 4*32K=128k bytes<li>signal FlashRomBankReg: STD_LOGIC_VECTOR (2 downto 0);--Flash Rom bank switch reg, 8 banks, 8*16K=128k bytes<li>--Rd Sample<li>signal RdSample:std_logic; --for Rd Sample<li>--WR Sample <li>signal WrSample0:std_logic; --Wr for Sample <li>signal WrSample1:std_logic; <li>signal WrSample2:std_logic; <li>signal WrSample3:std_logic;<li>signal WrSample4:std_logic; <li>signal WrSample5:std_logic;<li>--Wr Sample output<li>signal Wr_en:std_logic; <li>--Clr Sample <li>signal ClrSample0:std_logic; -- for Clr Sample <li>signal ClrSample1:std_logic; <li>signal ClrSample2:std_logic; <li>signal ClrSample3:std_logic;<li>signal ClrSample4:std_logic; <li>signal ClrSample5:std_logic;<li>signal ClrSample6:std_logic; <li>signal ClrSample7:std_logic; <li>signal ClrSample8:std_logic;<li>signal ClrSample9:std_logic; <li>--Clr Sample output<li>signal Clr_en:std_logic;<li>------------------------------------------------------------------------------<li>--output Reg<li>signal PinaReg:std_logic; <li>begin<li>--------------------------------------------<li>--Sample Clr signal<li>ClrSample_p:process(Clk)<li>begin<li> if Clk'event and Clk='1' then<li>ClrSample0<=Clr;<li>ClrSample1<=ClrSample0;<li>ClrSample2<=ClrSample1;<li>ClrSample3<=ClrSample2;<li>ClrSample4<=ClrSample3;<li>ClrSample5<=ClrSample4;<li>ClrSample6<=ClrSample5;<li>ClrSample7<=ClrSample6;<li>ClrSample8<=ClrSample7;<li>ClrSample9<=ClrSample8;<li> end if;<li>end process;  <li>---------------------------------------<li>--Clr Enable Signal<li>Clr_en_p:process(Clk)<li>begin  <li> if Clk'event and Clk='1' then<li>if  ClrSample0='1' and ClrSample1='1'<li> and ClrSample2='1' and ClrSample3='1'<li> and ClrSample4='1' and ClrSample5='1'<li> and ClrSample6='1' and ClrSample7='1'<li> and ClrSample8='1' and ClrSample9='1' then<li> Clr_en<='1';<li>else<li> Clr_en<='0';<li>end if;<li> end if;<li>end process;   <li>------------------------------------------------<li>--sample ALE signal <li>ALE_p:process(Clk)<li> begin<li>if Clk'event and Clk='1' then<li> if Clr_en='1' then<li>  ALE_Sample<='0';<li> else<li>  ALE_Sample<=ALE;<li> end if;<li>end if;<li>end process;<li>-------------------------------------------------  <li>--Address Latch <li>Address_p:process(Clk)<li> begin<li>if Clk'event and Clk='1' then<li> if Clr_en='1' then<li> Addr<="0000000000000000";<li> elsif ALE_Sample='1' then<li>  Addr<=P2&amp0;<li> end if;<li>end if;<li> end process;    <li>-------------------------------------<li>--Sample Wr<li>WrSample_p:process(Clk)<li>begin<li> if Clk'event and Clk='1' then<li>if Clr_en='1' then<li> WrSample0<='1';<li> WrSample1<='1';<li> WrSample2<='1';<li> WrSample3<='1';<li> WrSample4<='1';<li> WrSample5<='1';<li>else<li> WrSample0<=Wr;<li> WrSample1<=WrSample0;<li> WrSample2<=WrSample1;<li> WrSample3<=WrSample2;<li> WrSample4<=WrSample3;<li> WrSample5<=WrSample4;<li>end if;<li> end if;<li>end process; <li>---------------------------------------<li>--internal Wr enable signal<li>WrEn_p:process(WrSample0,WrSample1,WrSample2,WrSample3,WrSample4,WrSample5)<li>begin<li> if (WrSample0='0' andWrSample1='0'<li>and WrSample2='0' and WrSample3='0'<li>and WrSample4='1'and WrSample5='1')then<li>Wr_en<='1';<li> else<li>Wr_en<='0';<li> end if;<li>end process;   <li>----------------------------------------<li>--Rd Sample<li>RdSample_p:process(Clk)<li>begin<li> if Clk'event and Clk='1' then<li>if Clr_en='1' then<li> RdSample<='1';<li>else<li> RdSample<=Rd;<li>end if;<li> end if;<li>end process;<li> <li>-----------------------------------<li>--Flash Rom Chip select signal<li>CS_Flash_p:process(Addr)<li>begin<li> if Addr(15 downto 14)="10" then    --Address:8000h--BFFFh<li> nCsFlashRam<='0';<li> else<li>nCsFlashRam<='1';<li> end if;<li>end process;<li>-----------------------------------<li>-- 8255 Chip select signal<li>cs8255_p:process(Addr)<li>begin<li>if Addr(15 downto 2)="11000000000000" then--C000h--C003h <li> nCS8255<='0';<li>else<li> nCS8255<='1';<li>end if;<li> end process;  <li>-----------------------------------<li>----------------------------------- <li>-- Ram Bank Switch Reg <li>Ram_bank_p:process(Clk)<li>begin   <li> if Clk'event and Clk='1' then<li>if Clr_en='1' then<li>  RamBankReg<="00";<li>elsif Addr="1100000000000100" and Wr_en='1' then  --Address:C004h<li>   RamBankReg<=P0(1 downto 0);<li>end if;<li> end if;<li>end process;<li>RamBank<=RamBankReg;   <li>----------------------------------<li>----------------------------------<li>--Flash Rom Switch Reg<li>Flash_bank_p:process(Clk)<li>begin  <li> if Clk'event and Clk='1' then<li>if Clr_en='1' then<li> FlashRomBankReg<="000";<li>elsif Addr="1100000000000101"and Wr_en='1' then  --Address:C005h<li> FlashRomBankReg<=P0(2 downto 0);<li>end if;<li> end if;<li>end process;<li>FlashRomBank<=FlashRomBankReg; <li>--------------------------------<li>--------------------------------<li>--Rd process<li>-- now just two in-builde register<li>Rd_p:process(RdSample,Addr,RamBankReg,FlashRomBankReg)<li>begin<li> if  Addr="1100000000000100"and RdSample='0' then  --C004h<li> P0<="000000"&RamBankReg;<li> elsif Addr="1100000000000101"and RdSample='0' then  --C005h<li&gt0<="00000"&FlashRomBankReg;<li> else <li&gt0<="ZZZZZZZZ";<li> end if;<li>end process;  <li>-------------------------------  <li&gtina_p:process(Clk)<li>begin<li> if Clk'event and Clk='1' then<li>if Clr_en='1' then<li> PinaReg<='0';<li>elsif Addr="1100000000000110"and Wr_en='1' then  --C006h <li> PinaReg<=P0(0);<li>end if;<li> end if;<li>end process; <li&gtina<=PinaReg;  <li>end cpldbus51;<li><li> </ol><em onclick="copycode($('code_i51'));">复制代码</em>