有用过mst703驱动群创10.2寸液晶屏AT102TN03的吗？

a06114113 · 发表于 2017-10-7 16:34:06

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最近用mst703驱动群创10.2寸液晶屏AT102TN03，程序用的是mstar提供的公版maria软件。目前已经可以通过按键开关机了，但就是一直白屏。因程序里没有提供10.2寸屏的头文件，是我自己拿别的头文件改的，因此判断是屏参数配置错误。做过的帮忙看下哪里出了问题（估计是在上电时序和一堆寄存器参数那块），要是能发我一份就最好了

。

#include "ms_reg.h"
#ifndef _PNL_AT102TN03_H_
#define _PNL_AT102TN03_H_
#include "devvd.h"
#define PanelName "PnlAT102TN03" //
#define WidePanel 0 //
#define PanelDither 8 //
#define PANEL_TTL 1
#define PANEL_DIGITAL_TCON 0
#define PANEL_ANALOG_TCON 0
#define PANEL_LVDS_TI_MODE 0
#define PANEL_SWAP_LVDS_POL 1
#define PANEL_SWAP_LVDS_CH 0
#define PanelSwapRB (0xFF)
#define PanelSwap8BitML 0//0x0F
#define PanelSwap6BitML 0
#define PanelDClkDelay 0
#define PanelInvDE 0
#define PanelInvDClk (0x0F)
#define PanelInvHSync 0
#define PanelInvVSync 0
// driving current setting 0==>4mA, 1==>6mA, 2==>8mA ,3==>12mA
#define PanelDCLKCurrent 0 // Dclk current
#define PanelDECurrent 0 // DE signal current
#define PANELHSCURRENT 0 // HSYNC current
#define PANELVSCURRENT 0 // VSYNC current
#define PANELBMCURRENT 0 // B data High-Nibble current
#define PANELBLCURRENT 0 // B data Low-Nibble current
#define PANELGMCURRENT 0 // G data High-Nibble current
#define PANELGLCURRENT 0 // G data Low-Nibble current
#define PANELRMCURRENT 0 // R data High-Nibble current
#define PANELRLCURRENT 0 // R data Low-Nibble current
#define PANELADCLKCURRENT 0 // Analog Panel DCLK current
#if SYSTEM_BOOT_UP_QUICKLY_ENABLE
#define PanelOnTiming1 20//20 // time between panel & data while turn on power
#define PanelOnTiming2 20//20 // time between data & back light while turn on power
#define PanelOffTiming1 2 // time between back light & data while turn off power
#define PanelOffTiming2 2 // time between data & panel while turn off power
#else
#define PanelOnTiming1 100 //100 time between panel & data while turn on power
#define PanelOnTiming2 100 //100 time between data & back light while turn on power
#define PanelOffTiming1 20 //20 time between back light & data while turn off power
#define PanelOffTiming2 20 //20 time between data & panel while turn off power
#endif
#define PanelHSyncWidth 40
#define PanelHSyncBackPorch 44
#define PanelVSyncWidth 4
#define PanelVSyncBackPorch 34
#define PANEL_DE_VSTART 0
#define PanelHStart (PanelHSyncWidth+PanelHSyncBackPorch) //88
#define PanelVStart (PanelVSyncWidth+PanelVSyncBackPorch) //38
#define PanelWidth 800
#define PanelHeight 480
#define PanelHTotal 1080
#define PanelVTotal 525
#define PanelVdeEnd PanelHeight
#define PanelVSiEnd PanelHeight
#define PanelMinHTotal 1080
#define PanelDCLK (((DWORD)PanelHTotal*PanelVTotal*60)/1000000)
///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////
// PTC Mode setting
#define SET_PTC_MODE1 0x8C // PTC_MODE1(0xD0)
#define SET_PTC_MODE2 0x46
#define SET_PTC_MODE2_NOR 0x36 // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE2_INV 0x31 // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE3 0x82 // PTC_MODE3(0xD2)
// PTC Timming Setting
#define SET_FRP_TRAN 0x02 // GPO_FRP_TRAN(0xDC)
#define SET_STH_START 0x35 // GPO_STH_START(0xDD) ORG:0x2C
#define SET_STH_WIDTH 0x01 // GPO_STH_WIDTH(0xDE)
#define SET_OEH_START 0x00 // GPO_OEH_START(0xDF)
#define SET_OEH_WIDTH 0x2C // GPO_OEH_WIDTH(0xE0)
#define SET_OEV_START 0x6C // GPO_OEV_START(0xE1)
#define SET_OEV_WIDTH 0x29 // GPO_OEV_WIDTH(0xE2)
#define SET_CKV_START 0x2A // GPO_CKV_START(0xE3)
#define SET_CKV_START2 0x00 // GPO_CKV_START2(0xE4)
#define SET_CKV_WIDTH 0x1C // GPO_CKV_WIDTH(0xE5)
#define SET_STV_LINE_TH 0x44 // GPO_STV_LINE_TH(0xE6)
#define SET_STV_START 0x6F // GPO_STV_START(0xE7)
#define SET_STV_WIDTH 0x00 // GPO_STV_WIDTH(0xE8)
#define SET_OEV2_START 0x00 // GPO_OEV2_START(0xE9)
#define SET_OEV3_START 0x00 // GPO_OEV3_START(0xEA)
#define SET_H_ST_DLY_L 0x00 // H_ST_DLY_L(0xEB)
#define SET_H_ST_DLY_H 0x00 // H_ST_DLY_H(0xEC)
#define SET_CLK_DLY_SYNC_OUT 0x00 // CLK_DLY_SYNC_OUT(0xED)
#define SET_CKV_END2 0x00 // GPO_CKV_END2(0xEE)
#define SET_Q1H 0x00 // Q1H_SETTING(0xEF)
#define SET_OEV2_WIDTH 0x54 // GPO_OEV2_WIDTH(0xCD)
#define SET_OEV3_WIDTH 0x54 // GPO_OEV3_WIDTH(0xCE)
#define SET_OEV_DELTA 0x54 // GPO_OEV_DELTA(0xCF)
// VCOM setting
#define SET_BVOM_DC 0xA0 //DEF_VCOM_DC // BVOM_DC(0x43)
#define SET_BVOM_OUT 0xA0 //DEF_VCOM_AC // BVOM_OUT(0x44)
// DAC setting
#define SET_VDAC_ADJ1 0x00 // VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2 0x00 // VDAC_ADJ2(0xAB)
// Video decoder
#define _656_PLL_VALUE 0x83 //BK2_9D_DPL_NSPL_HIGH
#define COCTRL1_VALUE 0x20
#define SVD_EN_VALUE0 0x40 //BK2_1A_SVD_EN
#define BK1_7B_TERM_SEL_VALUE 0xE4
#define BK1_7C_CROING_VALUE 0x64
#define PANEL_SYNC_MODE_1 0
#define ENABLE_VSYNC_CTL_AUTO_H_TOTAL 0// 1
#define ENABLE_CHECK_AUTO_H_TOTAL 0// 1
#define ENABLE_OVER_SCAN 1
#define VD_OVER_SCAN_H 00 // 1.0%
#define VD_OVER_SCAN_V 24 // 1.0%
#define BK0_03_SYNC_Sample_Edge 0x98//0x98
#define PANEL_LOCK_Y_LINE 2
#ifdef _VDCaptureSetting_
code _CaptureVideoWinType tMsVDCapture[SIG_NUMS] = // For internal VD
{
{0x78, 0x14, 1340, 480}, // NSTC
{0x7D, 0x0E, 1340, 576}, // PAL
{0x85, 0x1A, 1340, 576}, // SECAM
{0x85, 0x1A, 1340, 480}, // NTSC-443
{0x85, 0x1A, 1340, 480}, // PAL-60
{0x85, 0x1A, 1340, 480}, // PAL-M
{0x85, 0x1A, 1340, 576}, // PAL-Nc
};
code _CaptureSvideoWinStartType tSvideoCaptureStart[SIG_NUMS] = // For internal VD
{
{0x4d, 0x02}, // NSTC
{0x5f, 0x0f}, // PAL
{0x5f, 0x0f}, // SECAM
{0x4d, 0x02}, // NTSC-443
{0x5f, 0x0f}, // PAL-60
{0x5f, 0x0f}, // PAL-M
{0x5f, 0x0f}, // PAL-Nc
};
#endif
#define FreeRunHTotal 0x4A7
#define PalHTotal 0x4A7
#define NtscHTotal 0x593
#ifdef EnableUseModeTbl
RegUnitType code tENDModeTbl[]=
{
{_END_OF_TBL_,0},
};
RegUnitType code tNtscModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code tPalModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
#if CCIR656_ENABLE
RegUnitType code tCCIR656_PalModeTbl[]=
{//Reg Vale
{BK0_05_SPRVST_L, 0x1e},
{BK0_06_SPRVST_H, 0x00},
{BK0_07_SPRHST_L, 0x45},
{BK0_08_SPRHST_H, 0x01},
{BK0_0B_SPRHDC_L, 0xc4},
{BK0_27_OPL_SET2, 0x36},
{BK0_30_SRH_L, 0x00},
{BK0_31_SRH_M, 0x36},
{BK0_32_SRH_H, 0xcb},
{BK0_34_SRV_M, 0x78},
{_END_OF_TBL_, 0x00},
};
RegUnitType code tCCIR656_NtscModeTbl[]=
{//Reg Vale
{BK0_05_SPRVST_L, 0x1e},
{BK0_06_SPRVST_H, 0x00},
{BK0_07_SPRHST_L, 0x45},
{BK0_08_SPRHST_H, 0x01},
{BK0_0B_SPRHDC_L, 0xb1},
{BK0_30_SRH_L, 0x00},
{BK0_31_SRH_M, 0x20},
{BK0_32_SRH_H, 0xc9},
{_END_OF_TBL_, 0x00},
};
#endif
#if VGA_ENABLE
RegUnitType code t640_480_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_72Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_56Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_72Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0B},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_60Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0E},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_70Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0E},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_75Hz_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0E},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
#endif
#if 0//YPBPR_ENABLE
RegUnitType code t576i_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x05},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t576p_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0a},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t480i_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x04},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t480p_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x08},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t720p_50Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0c},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t720p_60Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0b},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1080i_50Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x06},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1080i_60Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x07},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1080p_50Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x06},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1080p_60Hz_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x07},
{BK0_00_REGBK,REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
#endif
RegUnitType code tTVSnowModeTbl[]=
{//Reg Vale
/*
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_33_SRV_L,0x88},
{BK0_34_SRV_M,0xA1},
{BK0_35_SRV_H,0x88},
{BK0_40_VFDEST_L,0x10},
{BK0_41_VFDEST_H,0x00},
{BK0_44_VFDEEND_L,0xFE},
{BK0_45_VFDEEND_H,0x01},
{BK0_4A_SIVEND_L,0xFE},
{BK0_4B_SIVEND_H,0x01},
{BK0_57_OSCTRL1,0xD6}, */
{_END_OF_TBL_, 0x00},
};
RegUnitType code tFreeRunModeTbl[]=
{//Reg Vale
/*
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_27_OPL_SET2, 0x23},
{BK0_40_VFDEST_L,0x00},
{BK0_41_VFDEST_H,0x00},
{BK0_44_VFDEEND_L,0xE9},
{BK0_50_VSST_L, 0xF2}, // vsync start position
{BK0_51_VSST_H, 0x0A},
*/
{_END_OF_TBL_, 0x00},
};
#endif
//*******************************************************************
//Ace setting
#define CbGain 0x80
#define CrGain 0x80
#define RedGain 0x80//127
#define GreenGain 0x80//130
#define BlueGain 0x80//126
#define INIT_VIDEO_CONTRAST_X0 80
#define INIT_VIDEO_CONTRAST_X1 100
#define INIT_VIDEO_CONTRAST_X2 140
#define INIT_VIDEO_CONTRAST_X3 150
#define INIT_VIDEO_CONTRAST_X4 160
#define INIT_VIDEO_BRIGHTNESS_X0 0x50
#define INIT_VIDEO_BRIGHTNESS_X1 0x70
#define INIT_VIDEO_BRIGHTNESS_X2 0x80
#define INIT_VIDEO_BRIGHTNESS_X3 0x90
#define INIT_VIDEO_BRIGHTNESS_X4 0xc0
#define INIT_VIDEO_SATURATION_X0 0
#define INIT_VIDEO_SATURATION_X1 60
#define INIT_VIDEO_SATURATION_X2 120
#define INIT_VIDEO_SATURATION_X3 150
#define INIT_VIDEO_SATURATION_X4 200
#define INIT_SV_CONTRAST_X0 80
#define INIT_SV_CONTRAST_X1 100
#define INIT_SV_CONTRAST_X2 128
#define INIT_SV_CONTRAST_X3 150
#define INIT_SV_CONTRAST_X4 180
#define INIT_SV_BRIGHTNESS_X0 0x50
#define INIT_SV_BRIGHTNESS_X1 0x70
#define INIT_SV_BRIGHTNESS_X2 0x80
#define INIT_SV_BRIGHTNESS_X3 0x90
#define INIT_SV_BRIGHTNESS_X4 0xc0
#define INIT_SV_SATURATION_X0 0
#define INIT_SV_SATURATION_X1 80
#define INIT_SV_SATURATION_X2 168
#define INIT_SV_SATURATION_X3 20
#define INIT_SV_SATURATION_X4 255
#define INIT_VGA_CONTRAST_X0 80
#define INIT_VGA_CONTRAST_X1 100
#define INIT_VGA_CONTRAST_X2 128
#define INIT_VGA_CONTRAST_X3 150
#define INIT_VGA_CONTRAST_X4 180
#define INIT_VGA_BRIGHTNESS_X0 0x50
#define INIT_VGA_BRIGHTNESS_X1 0x70
#define INIT_VGA_BRIGHTNESS_X2 0x80
#define INIT_VGA_BRIGHTNESS_X3 0x90
#define INIT_VGA_BRIGHTNESS_X4 0xc0
#define INIT_YPBPR_CONTRAST_X0 80
#define INIT_YPBPR_CONTRAST_X1 100
#define INIT_YPBPR_CONTRAST_X2 128
#define INIT_YPBPR_CONTRAST_X3 150
#define INIT_YPBPR_CONTRAST_X4 180
#define INIT_YPBPR_BRIGHTNESS_X0 0x40
#define INIT_YPBPR_BRIGHTNESS_X1 0x60
#define INIT_YPBPR_BRIGHTNESS_X2 0x80
#define INIT_YPBPR_BRIGHTNESS_X3 0xa0
#define INIT_YPBPR_BRIGHTNESS_X4 0xc0
#define INIT_YPBPR_SATURATION_X0 0
#define INIT_YPBPR_SATURATION_X1 60
#define INIT_YPBPR_SATURATION_X2 128
#define INIT_YPBPR_SATURATION_X3 150
#define INIT_YPBPR_SATURATION_X4 200
#define INIT_MSVD_COMB_YGAIN 0x85 //BK3_13
#define INIT_MSVD_COMB_CbGAIN 0x88 //BK3_14
#define INIT_MSVD_COMB_CrGAIN 0x80// 0x80 //BK3_15
#define INIT_MSVD_COMB_CONTRAST 0x94//0x9A //BK3_63
#define INIT_MSVD_COMB_BRIGHTNESS 0x96 //BK3_64
#define INIT_MSVD_COMB_SATURATION 0x90//0xA0 //BK3_65
#define INIT_MSVD_TV_BRIGHTNESS 0x0CE // bk2_38[6] bk2_3a[7:0] MAXVALUE=0X1FF
#ifdef EnableUseGammaTbl
BYTE code tGammaTableNormal[3][33]=
{
{
0x00,0x03,0x07,0x0C,0x12,0x19,0x20,0x28,0x31,0x3A,0x43,
0x4D,0x57,0x61,0x6B,0x75,0x80,0x8B,0x95,0x9F,0xA9,0xB3,
0xBD,0xC6,0xCF,0xD7,0xDF,0xE6,0xEC,0xF2,0xF7,0xFB,0xFF,
},
{
0x00,0x03,0x07,0x0C,0x12,0x19,0x20,0x28,0x31,0x3A,0x43,
0x4D,0x57,0x61,0x6B,0x75,0x80,0x8B,0x95,0x9F,0xA9,0xB3,
0xBD,0xC6,0xCF,0xD7,0xDF,0xE6,0xEC,0xF2,0xF7,0xFB,0xFF,
},
{
0x00,0x03,0x07,0x0C,0x12,0x19,0x20,0x28,0x31,0x3A,0x43,
0x4D,0x57,0x61,0x6B,0x75,0x80,0x8B,0x95,0x9F,0xA9,0xB3,
0xBD,0xC6,0xCF,0xD7,0xDF,0xE6,0xEC,0xF2,0xF7,0xFB,0xFF,
},
};
#endif
#ifdef EnableColorMatrix
short code tVideoColorCorrectionMatrix[][3]=
{
0x0441,-0x0041, 0x0000, 0x0030, 0x039E, 0x0032,-0x0045, 0x0092,
0x03B3,-0x0369, 0x01AB,-0x051B, 0x0012,-0x01D9, 0x0777,-0x0378,
-0x0735, 0x017A, 0x019E,-0x026E, 0x0274, 0x0687,-0x07A6, 0x0280,
-0x0831, 0x0100,-0x0001, 0x0001,-0x0001, 0x0000,-0x0064,-0x0032,
};
#endif
#ifdef _EnableFCC_
RegUnitType code tInitializeFCC[] =
{
/////////////////////////////////////////////////
// Initialize MACE table
/////////////////////////////////////////////////
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_56_FCC_CB_1T, 0x74}, // FCC_
{BK1_57_FCC_CR_1T, 0x9B}, // FCC_
{BK1_58_FCC_CB_2T, 0x6E}, // FCC_
{BK1_59_FCC_CR_2T, 0xAC}, // FCC_
{BK1_5A_FCC_CB_3T, 0xA5}, // FCC_
{BK1_5B_FCC_CR_3T, 0x69}, // FCC_
{BK1_5C_FCC_CB_4T, 0x5A}, // FCC_
{BK1_5D_FCC_CR_4T, 0x9A}, // FCC_
{BK1_5E_FCC_CB_5T, 0x5A}, // FCC_
{BK1_5F_FCC_CR_5T, 0x75}, // FCC_
{BK1_60_FCC_CB_6T, 0xB0}, // FCC_
{BK1_61_FCC_CR_6T, 0x48}, // FCC_
{BK1_62_FCC_CB_7T, 0x64}, // FCC_
{BK1_63_FCC_CR_7T, 0xD8}, // FCC_
{BK1_64_FCC_CB_8T, 0x80}, // FCC_
{BK1_65_FCC_CR_8T, 0x80}, // FCC_
{BK1_66_FCC_CB_9T, 0x80},//0x88}, // FCC_
{BK1_67_FCC_CR_9T, 0x80},// FCC_ A0
{BK1_68_FCC_WIN1, 0xA6}, // FCC_
{BK1_69_FCC_WIN2, 0xBA}, // FCC_
{BK1_6A_FCC_WIN3, 0xFB}, // FCC_
{BK1_6B_FCC_WIN4, 0x73}, // FCC_
{BK1_6C_FCC_WIN5, 0xFB}, // FCC_
{BK1_6D_FCC_WIN6, 0xFB}, // FCC_
{BK1_6E_FCC_WIN7, 0xFF}, // FCC_
{BK1_6F_FCC_WIN8, 0x6A}, // FCC_
{BK1_70_FCC_WIN9, 0x00}, // FCC_
{BK1_71_FCC_Y_TH, 0xFF}, // FCC_
{BK1_72_FCC_K1K2, 0x60}, // FCC_
{BK1_73_FCC_K3K4, 0xFE}, // FCC_
{BK1_74_FCC_K5K6, 0xCB}, // FCC_
{BK1_75_FCC_K7K8, 0x85}, // FCC_
// {BK1_76_FCC_CTRL, 0x2F}, // FCC_
// {BK1_77_APP_CTRL, 0x7E}, // FCC_
{BK1_78_PEAK_BAND1, 0x1D}, // FCC_
{BK1_79_PEAK_BAND2, 0x58}, // FCC_
// {BK1_7A_LTI, 0x98}, // FCC_
{BK1_7D_CTI,0x78},
{BK1_7E_VIP_Y_CTRL,0x00},
{BK1_7F_MAX_PIX, 0x80}, // MAX_PIX
{BK1_80_MIN_PIX, 0x40}, // MIN_PIX
// {BK1_81_EGE_BAND1_POS,0x40},
// {BK1_82_EGE_BAND1_NEG,0x60},
// {BK1_84_EGE_BAND2_NEG,0x60},
// {BK1_85_M_BRI,0x08},
// {BK1_86_EGE_LTI_POS,0x10},
// {BK1_87_EGE_LTI_NEG,0x20},
// {BK1_88_YC_LPF, 0xBC},
{BK1_89, 0x00},
// {BK1_8A, 0x23},
{BK1_8B, 0x43},
{BK1_8C, 0xFF},
{BK1_8D, 0xAE},
{BK1_8E, 0x36},
{BK1_8F, 0x01},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00}
};
RegUnitType code tVideoFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_77_APP_CTRL, 0x00}, //7E FCC_
{BK1_85_M_BRI,0x00},
{BK1_88_YC_LPF, 0xBC}, //0xBC
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00}
};
#if VGA_ENABLE
RegUnitType code tPCFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_77_APP_CTRL, 0}, // FCC_
{BK1_85_M_BRI,0},
{BK1_88_YC_LPF, 0},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00}
};
#endif
RegUnitType code t_AVInitializeFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_76_FCC_CTRL, 0x6F}, // FCC_
{BK1_7A_LTI, 0x98}, // FCC_
{BK1_7C_CROING,0x42},
{BK1_81_EGE_BAND1_POS,0x40},
{BK1_82_EGE_BAND1_NEG,0x60},
{BK1_84_EGE_BAND2_NEG,0x60},
{BK1_86_EGE_LTI_POS,0x10},
{BK1_87_EGE_LTI_NEG,0x20},
{BK1_88_YC_LPF, 0x80},
{BK1_8A, 0x23},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t_SVInitializeFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_7A_LTI, 0x08}, // FCC_
{BK1_7C_CROING,0xFF},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t_TVInitializeFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_76_FCC_CTRL, 0x2D},
{BK1_7A_LTI, 0x90},
{BK1_7C_CROING,0x42},
{BK1_81_EGE_BAND1_POS,0x00},
{BK1_82_EGE_BAND1_NEG,0x00},
{BK1_84_EGE_BAND2_NEG,0x00},
{BK1_86_EGE_LTI_POS,0x00},
{BK1_87_EGE_LTI_NEG,0x00},
{BK1_88_YC_LPF, 0x9C},
{BK1_8A, 0x43},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
#endif // _EnableFcc_
#endif