关于在capture cis 生成网表后导入PADS LAYOUT 的报错。请不吝赐

2dmin

我在生成网表后，导入pads layout， 结果报告如下错误：% [- ~' S* ]0 j+ I) F
Can't find part Type item < XTAL_HC49SMT >
Y1     XTAL_HC49SMT# B: K2 P0 H; m
Can't find part Type item < XTAL_HC49SMT >2 y3 ^6 q$ _/ B[+ R
Y2     XTAL_HC49SMT
Can't find part Type item < XTAL_HC49SMT >- D: w2 M! O: v) @
Y3     XTAL_HC49SMT
*Part name not found U13
U13.1 R9.1 C45.2 R13.2 R14.1
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal N13564200 p8 a& [4 W" U) g* C
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal XT2_PHY
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal USB_D+2
*Part name not found Y13 P- v0 O5 o; j" m
Y1.2 U6.1 C28.1 J3.1 J4.1 J5.1. I! y$ g5 pT, G0 y
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal OSC15 A; B1 T: V8 w8 K
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal CRS_PHY# F' T* N" i, \! L
*Part name not found Y2
U5.34 Y2.2 C41.2
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal RTCK1
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal VDD_PHY# D, X! I! O* o* U' b! Z
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal TXD1_PHY
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal USB_OTG_IDK0 x* e5 }# c2 s$ f! G# C
除了上述报错元件不能导入，可以导入其它元件。我的部分PCB封装在自己建的pads库里，还用了些常用的自带库。请问3 ?! I* m1 y7 e$ [1 j# A. O
这些错是什么原因造成的？我看了一天了也没头绪。2 Bu: z3 f! P4 a7 b' H
多谢各位看完。$ M! {; h2 A( g2 b$ p
我会把整个设计放在附件里。
再谢。










LPC2478MATRIX-Sep-02-2008.zip



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