DRC检查问题

2dmin

DRC - (Final DRC)
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        08:00 AM Tuesday, September 09, 2008
   Job Name: D:\prj\080906\PCB\22V1.0.pcb


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  PROXIMITY* {m4 T& I1 p. u
  ---------7 v" N+ {1 e& e+ X
  
  Use DRC Window       : NO

/ d% Z8 i' s5 Q1 Z, u) x
  Disable Same Cell Pad-Pad Checks : NO# a; ^" {3 b+ s
" E% m1 D4 E$ n: L3 a; |; k

  Enable Same Net Pad-Pad Checks : NO
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  # r) @, i7 X2 ^2 `+ T, d" N& m
  Layers Specifed To Check   : Layer 1- ^) d, W% R1 u' z; Q
             Layer 2# r1 E: N- a& m, e/ P5 Y


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  Net Class Clearances And Rules' Q@( W/ h' M! n# Z# ?' r
  ------------------------------
2 h0 r1 bO3 i" p
  >>Components Top TO Components Top
    Hazards Found : 4

  Traces Layer 1 TO Traces Layer 11 |1 y+ E2 M6 A4 n) N5 m0 y1 A
    No Hazards.
$ J( e' ?& q0 J8 s7 x" X4 ~) }, J5 o
  Traces Layer 1 TO Part Pads SMD Layer 1
    No Hazards.
* Z) f- u' U! Z
  Traces Layer 1 TO Part Pads Thru Layer 1
    No Hazards.

  Traces Layer 1 TO Part Holes Layer 1
    No Hazards.7 Y' ^7 \) D6 `* d% U1 w
8 ~( l. r% J- k* o9 C2 D" p5 Z, K
  Traces Layer 1 TO Via Pads Layer 1
    No Hazards.& l! G0 a, d( S0 w% T
o5 C) f7 r- m) E! V
  Traces Layer 1 TO Via Holes Layer 1
    No Hazards.& H8 n9 E" B% Y2 n

  Part Pads SMD Layer 1 TO Part Pads SMD Layer 1
    No Hazards.

  Part Pads SMD Layer 1 TO Part Pads Thru Layer 1
    No Hazards.
+ a, \* {- H1 h|& f1 z" g% _- j
  Part Pads SMD Layer 1 TO Part Holes Layer 15 M- [' }! T+ p
    No Hazards.$ v. b5 |' c; v2 N' U* N6 {
' d! ]6 \, p4 b' g+ W/ {8 o
  Part Pads SMD Layer 1 TO Via Pads Layer 1
    No Hazards.* r2 y* x& u+ ~; V0 ]( U

  Part Pads SMD Layer 1 TO Via Holes Layer 1& V7 b& j3 `' c& w/ d' b9 J
    No Hazards.1 p1 d1 _5 X$ D, V. N1 U

  Part Pads Thru Layer 1 TO Part Pads Thru Layer 1
    No Hazards.
$ }& ]; a, H, [3 |0 y$ _
  Part Pads Thru Layer 1 TO Part Holes Layer 1; D+ b7 k" ?' V% y( NZ1 {3 s
    No Hazards.: k) K; V; L) p3 Z! Z

  Part Pads Thru Layer 1 TO Via Pads Layer 1/ o9 q* g/ g7 v
    No Hazards.2 S, w( O5 P" W, @

  Part Pads Thru Layer 1 TO Via Holes Layer 1
    No Hazards.9 p@4 g! S6 p: e# c1 i
3 }% F4 T. v$ b: j2 p( z
  Part Holes Layer 1 TO Via Pads Layer 10 ?0 C% A$ c/ \( d# f2 a7 C5 \
    No Hazards.
; D7 o4 a% L6 ?
  Part Holes Layer 1 TO Via Holes Layer 14 j3 Q* c; B7 T) t3 j$ ~4 u
    No Hazards.' j7 C( k- ~& E( {0 X, I# Y! b
' S! A& N$ H; x/ C& P/ A
  Via Pads Layer 1 TO Via Pads Layer 1% o" W6 s5 q3 U' `7 b6 p; z
    No Hazards.

  Via Pads Layer 1 TO Via Holes Layer 1; e- Z. {4 D/ f& d" J
    No Hazards.

  Via Holes Layer 1 TO Via Holes Layer 11 `% H. t1 y$ y5 Q5 q
    No Hazards.6 D2 P( i5 w# ?% R0 L0 iw
( e2 f6 S7 z3 j. }* O0 ]+ n) F4 a
  Traces Layer 2 TO Traces Layer 2; `7 w3 G1 N' A7 _/ {3 |0 N
    No Hazards.

  Traces Layer 2 TO Part Pads SMD Layer 2
    No Hazards.2 [5 J" W" T( I5 Z' p! z3 v

  Traces Layer 2 TO Part Pads Thru Layer 20 f! ~2 h1 ZJ$ s# e
    No Hazards.
8 o5 Q: S# E( c
  Traces Layer 2 TO Part Holes Layer 2
    No Hazards.

  Traces Layer 2 TO Via Pads Layer 2
    No Hazards.4 n9 E8 j. m2 y% E- j
; c- Dq: R. _, _" r0 U
  Traces Layer 2 TO Via Holes Layer 2
    No Hazards.

  Part Pads SMD Layer 2 TO Part Pads SMD Layer 2
    No Hazards.

  Part Pads SMD Layer 2 TO Part Pads Thru Layer 2
    No Hazards.

  Part Pads SMD Layer 2 TO Part Holes Layer 2
    No Hazards., F! d3 {3 W& q8 W2 ~5 X: {! ~- ~

  Part Pads SMD Layer 2 TO Via Pads Layer 2
    No Hazards.
* @' [# Z+ x2 i, J# f. I# m
  Part Pads SMD Layer 2 TO Via Holes Layer 2
    No Hazards.1 R/ ~7 S+ Y: K6 v; C" v2 _

  Part Pads Thru Layer 2 TO Part Pads Thru Layer 2
    No Hazards.6 YH0 E4 |" s. S( w+ a% D
5 N1 Q) k7 g4 X" c
  Part Pads Thru Layer 2 TO Part Holes Layer 2
    No Hazards.$ T; q# V. C0 M, F: t
. _. {( U) P4 s- n7 X, M5 J3 r5 J9 Q
  Part Pads Thru Layer 2 TO Via Pads Layer 2
    No Hazards.
+ {, r1 L) i, v9 j|7 j6 Y
  Part Pads Thru Layer 2 TO Via Holes Layer 2: l" K@0 i" M% c& a
    No Hazards.1 y( |8 `4 j* T4 g1 |
! p( Y) \9 e( u: a' _
  Part Holes Layer 2 TO Via Pads Layer 2& n& F" o( K) G* _, G% o
    No Hazards.( J$ h/ E+ u! ]- [& T1 K

  Part Holes Layer 2 TO Via Holes Layer 2
    No Hazards.

  Via Pads Layer 2 TO Via Pads Layer 26 w8 N, r; C& t) m
    No Hazards.
9 C, J. g6 t" c) q0 o( S
  Via Pads Layer 2 TO Via Holes Layer 2
    No Hazards.
8 l8 Y6 t$ D. D5 j; y) r! j4 A
  Via Holes Layer 2 TO Via Holes Layer 22 X5 r- R7 ~: H) C: p# U9 j
    No Hazards., A. G6 y% e9 F. H" M


  Total Hazards Found : 4




  Planes Clearances And Rules
  ---------------------------9 @# s" `8 O/ z) ]G
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  Positive Planes Layer 1 TO Part Pads SMD Layer 1
    No Hazards.8 R9 d5 S; Qi( ]( g

  Positive Planes Layer 1 TO Part Pads Thru Layer 11 [1 L/ H1 ?+ U' t
    No Hazards.

  Positive Planes Layer 1 TO Part Holes Layer 1
    No Hazards.& V7 g+ S, I0 i9 k1 ?0 P7 @

  Positive Planes Layer 1 TO Positive Planes Layer 1
    No Hazards.! m7 s4 h1 f* \) A8 z, z; p
4 k4 x9 S! m0 ?) P
  Positive Planes Layer 1 TO Route Border% a; X$ V% S2 H* [0 N
    No Hazards.
2 ~5 ~4 s/ V4 z" w8 t
  Positive Planes Layer 1 TO Traces Layer 1
    No Hazards.7 j9 X" h7 d; {N6 J
) p" u* b! A( B" A$ y) Z
  Positive Planes Layer 1 TO Via Pads Layer 1' U8 X* p, ]" ]1 k+ N: v
    No Hazards., O8 Y. Q/ p# l3 m; K

  Positive Planes Layer 1 TO Via Holes Layer 11 s/ W9 O4 X5 {( K/ Q2 Z+ yI/ U
    No Hazards.
3 R. Y, B3 p6 ^( O
  Positive Planes Layer 2 TO Part Pads SMD Layer 2/ a) h1 P6 }2 f3 U& \( Q& y7 j* CY5 N
    No Hazards.
5 l3 U6 c. T/ v, s" j4 F
  Positive Planes Layer 2 TO Part Pads Thru Layer 2, y) b: p# I, b% t2 S4 Q9 u, I9 \0 X" l
    No Hazards.
% z6 K7 t3 \2 d: B+ q
  Positive Planes Layer 2 TO Part Holes Layer 2
    No Hazards.
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  Positive Planes Layer 2 TO Route Border9 X4 `# x/ \0 S! i+ _7 l
    No Hazards.& e' p7 k% F1 R0 p) S

  Positive Planes Layer 2 TO Traces Layer 2
    No Hazards.

  Positive Planes Layer 2 TO Via Pads Layer 2
    No Hazards.n3 Q! q* m% k2 e$ D/ y& W7 w+ @

  Positive Planes Layer 2 TO Via Holes Layer 2
    No Hazards.* U$ C5 a- j& t' B3 Z9 M' v
8 l5 v$ W" B+ x) G" P+ Y

  Total Hazards Found : 0


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  Non-Net Class Element To Element Clearances And Rules
  -----------------------------------------------------
1 `0 F! vU$ ?, h+ k+ e! V2 j
  Route Border TO Via Pads Layer 1  Clearance: 0mm
    No Hazards.; f3 M4 y# B' o1 e2 O
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  Route Border TO Traces Layer 1  Clearance: 0mm
    No Hazards.

  Part Pads SMD Layer 1 TO Route Border  Clearance: 0mm7 F9 o" c3 g6 i
    No Hazards.5 O+ J( g! [4 q! b$ a+ z

  Part Pads Thru Layer 1 TO Route Border  Clearance: 0mm
    No Hazards.2 [w; ?4 b1 n# w$ \' X) X

  Board Outline TO Part Pads Thru Layer 1  Clearance: 0mm+ T$ \* f2 X8 ~, _7 U3 ^
    No Hazards.

  Board Outline TO Via Holes Layer 1  Clearance: 0mm4 |`4 ~% M9 c
    No Hazards.9 j% i" S& EW& @* c2 q# ^
- |: x5 r- L/ E/ s! `
  Board Outline TO Via Pads Layer 1  Clearance: 0mm9 N3 Z' PQ9 G( t, A8 {' [
    No Hazards.

  Board Outline TO Part Holes Layer 1  Clearance: 0mm# \! l9 }* I6 P+ }# S9 F$ h
    No Hazards.' d- C" L% S- _1 T) V3 n
2 f" n6 u* K. |& X- J4 i6 b! r
  >>Board Outline TO Placement Outlines Top  Clearance: 0.15mm% y, t. v$ _6 X5 Q% ~2 T
    Hazards Found : 28 H$ M) D3 O7 k9 An+ Y
& c4 m2 _& B" K4 _, ?
  Board Outline TO Part Pads SMD Layer 1  Clearance: 0mm
    No Hazards.
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  Board Outline TO Traces Layer 1  Clearance: 0mm
    No Hazards.7 o$ U3 r9 {" O+ H4 k# @
* T7 e8 T/ V7 F
  Route Border TO Via Pads Layer 2  Clearance: 0mm9 _( Z$ w' O, Z3 E8 D: g6 fS" g
    No Hazards.2 R2 d' p$ y3 l4 Z- H5 R. v

  Route Border TO Traces Layer 2  Clearance: 0mm
    No Hazards.1 \- A2 j3 ?- K8 @4 R; t8 f! r; B2 s

  Part Pads SMD Layer 2 TO Route Border  Clearance: 0mm
    No Hazards., S5 h: m& v' M' S4 J
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  Part Pads Thru Layer 2 TO Route Border  Clearance: 0mm
    No Hazards.. w/ _. u% Z2 s" m+ b8 ]

  Board Outline TO Part Pads Thru Layer 2  Clearance: 0mm
    No Hazards.$ p+ A! t; F; Gh$ @/ a8 h" C8 k+ R, z

  Board Outline TO Via Holes Layer 2  Clearance: 0mm4 F4 [% s! S/ U
    No Hazards.% o& f- r$ |) h0 c# f! v3 ?

  Board Outline TO Via Pads Layer 2  Clearance: 0mm. L9 Vk) t/ u9 f8 z- ~
    No Hazards.

  Board Outline TO Part Holes Layer 2  Clearance: 0mm& e5 G* l7 H: i7 J
    No Hazards.4 s' m) T' T2 f; w' K

  Board Outline TO Placement Outlines Bottom  Clearance: 0.15mm
    No Hazards.5 M0 S# L3 v9 V( Q7 H; ^+ n0 @

  Board Outline TO Part Pads SMD Layer 2  Clearance: 0mm
    No Hazards.
5 Z# {# j# i: g7 X2 a
  Board Outline TO Traces Layer 2  Clearance: 0mm# S* Y$ n6 K, V% Z
    No Hazards.
1 r( L/ p) j& P2 U$ D3 O- G

  Total Hazards Found : 2
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5 y/ T6 E$ z1 J! R: F
  Total Proximity Hazards Found : 6, c' G1 [+ v7 {: \- F4 x
) q\4 E. [1 C$ h5 M
. U2 {. e0 v; V& {?+ W5 H9 N
% ^8 E3 J! b5 l1 I5 S) d. a7 |

  ----------------------------/ ~4 _2 f' m/ u0 X- f( p
  CONNECTIVITY & SPECIAL RULES
  ----------------------------

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  Check For Unplaced Parts        : YES
  No Hazards.
+ @* w. I% _, f; o8 M; B5 |' C

  Check For Missing Parts       : YES
  No Hazards.
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* \% U; d* r( z! U
  Check Trace Hangers         : YES
  No Hazards.
& Q0 ~7 A% W( q9 U

  Check Trace Loops         : YES
  No Hazards.

5 ]2 ]* C4 I9 ~6 a; @
  Check Trace Widths          : YES
  Hazards Found : 122

) K1 d# @% N- B0 H5 A, j2 C( N
  Check Single Point Nets       : YESf8 a& F9 ~9 A" h" w
  Hazards Found : 1) K0 d& }, U8 |6 `3 \5 Y0 k; ]
; x2 p0 {0 c& }1 v% ?
' _: r0 Y& Z" q
  Check NonPlane Unrouted/Partially Routed Nets : YES
  No Hazards.


  Check Plane Unrouted/Partial Routed Nets  : YES% Z1 f2 y3 |) S
  No Hazards.

( Q& J: _( x; p% O3 v1 B8 W6 o
  Check Routed Plane Pins       : YES" C, ?& t# K4 Z" j3 B) w/ |+ t( E
  No Hazards.+ W* N& S& B% T7 i3 Z( C3 H
7 c# k9 ]! P5 O# z6 o
7 A& O5 `* s0 D9 H& n3 t# D
  Check Plane Islands         : YES
  No Hazards.% F6 V+ X. m2 h5 X" D

+ F3 v6 e9 \$ ]0 v4 i
  Check Dangling Vias/Jumpers       : YES
  No Hazards.

* z" N% o. \e: ]4 }: J
  Check Unrouted Pins         : YES
  No Hazards.

! c: v# d+ s4 y4 b
  Check Routed Non-Plated Pins      : YESr4 F1 Z2 H2 M' a
  No Hazards.
6 {% ]1 G$ g, q% G3 t/ e8 Z
1 i. {/ @1 a; p1 \: L' _& s
  Check Minimum Annular Ring      : NO, p7 g" S/ ?$ }
+ }) G: C: d+ x: J# j" I5 y
/ h% Z; r8 Z- h) Q4 O( y( j6 ]
  Check For Vias Under SMD Pads     : YES/ c/ n; V. R! e
  No Hazards.
! m. M1 ^9 N- v; ZN9 d. N( r

  Check For Vias Under Top Place Outlines   : YES
  Hazards Found : 52

, R6 ^3 o0 K5 `Z% ~6 j$ `
  Check For Vias Under Bottom Place Outlines  : YES
  Hazards Found : 10

6 l% K6 G8 ~9 |1 q" S1 e- e
  Check For Missing Conductive Pads     : NO( N7 v! `- f8 [% U! D& E) f


  Check For Missing Part Soldermask Pads  : NO

& X& c7 j$ n. \% a3 d( V* `4 U+ }
  Check For Missing Via Soldermask Pads   : NO
( F- T1 K2 F9 C
- x( f& _x; T# o) J
  Check For Missing Solderpaste Pads    : NO+ h: I" w1 ~' V) |7 a# L& n


{) z5 ~" \2 s9 k( \
  Total Connectivity/SpecialRules Hazards Found : 185



  ====================================================================


; w0 r8 C5 o# J
  Total DRC Hazards Found : 191J: f9 N" |o% d3 y
- ~/ [. F3 u6 D6 `8 OD


         08:00 AM Tuesday, September 09, 2008
( ~4 o2 T* N) {" }/ P5 f
2 B~6 G! F; y: S" ?s/ q" U: A, d9 b
以上是我做的板子的DRC结果，; O3 ?3 U5 p; X4 r7 W2 }
Check For Vias Under Top Place Outlines   : YES3 x& L* F$ l0 ]' E) [4 Q! t
  Hazards Found : 52+ M7 ?* j9 N0 W/ S( T9 S" X

+ F% `' [) G( i3 J3 K- p& w
  Check For Vias Under Bottom Place Outlines  : YES) Y$ c( E7 u0 U
  Hazards Found : 10

其中元件的放置框内打孔有报错，怎么能让它不报错呢？