请教：DRC报告文件上的错误

2dmin

PCB图进行DRC检测
选择其中Clearance Constraints Max/Min　Width Constraints Short Circuit Constraints 和Un-Routed Nets　Constraints 这几项（请大家帮忙看看是什么问题，我是自学的protel,尚不熟练，请指教！谢谢！）! D6 M% ]1 g1 n1 Q
结果如下：
Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )
Violation   Polygon Arc (6033.874mil,6670.183mil)TopLayerActual Width = 8mil
Violation   Polygon Arc (6019.943mil,6665.654mil)TopLayerActual Width = 8mil
Violation   Polygon Arc (6006.011mil,6661.126mil)TopLayerActual Width = 8mil
Violation   Polygon Arc (5992.08mil,6656.597mil)TopLayerActual Width = 8mil
……
More than 120 violations detected. DRC stopped!