Low-Power NoC for High-Performance SoC Design - FPGA/CPLD - 电子工程师俱

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Low-Power NoC for High-Performance SoC Design (System-on-Chip Design and Technologies)
By Hoi-Jun Yoo, Kangmin Lee, Jun Kyong Kim


  * Publisher: CRC
  * Number Of Pages: 304
  * Publication Date: 2008-03-31
  * ISBN-10 / ASIN: 1420051725
  * ISBN-13 / EAN: 9781420051728
  * Binding: Hardcover

Description:
Chip Design and Implementation from a Practical Viewpoint Focusing on chip implementation, Low-Power NoC for High-Performance SoC Design provides practical knowledge and real examples of how to use network on chip (NoC) in the design of system on chip (SoC). It discusses many architectural and theoretical studies on NoCs, including design methodology, topology exploration, quality-of-service guarantee, low-power design, and implementation trials. The Steps to Implement NoC The book covers the full spectrum of the subject, from theory to actual chip design using NoC. Employing the Unified Modeling Language (UML) throughout, it presents complicated concepts, such as models of computation and communication–computation partitioning, in a manner accessible to laypeople. The authors provide guidelines on how to simplify complex networking theory to design a working chip. In addition, they explore the novel NoC techniques and implementations of the Basic On-Chip Network (BONE) project. Examples of real-time decisions, circuit-level design, systems, and chips give the material a real-world context. Low-Power NoC and Its Application to SoC Design Emphasizing the application of NoC to SoC design, this book shows how to build the complicated interconnections on SoC while keeping a low power consumption.


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