tpd4e05u06瞬态抑制器TVS

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12453 812453 8ConnectorHDMI ControllerTPD4E05U06TPD4E05U06D0-D1+D1-D2+D2-CLK+CLKD0+GNDGNDGNDGNDD1+ D1- D2+ D2-GNDProductFolderOrderNowTechnicalDocumentsTools &SoftwareSupport &CommunityAn IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017TPDxE05U06 1, 4, 6 Channel ESD Protection Device for Super-Speed (Up to 6 Gbps)Interface11 Features1• IEC 61000-4-2 Level 4 ESD Protection– ±12-kV Contact Discharge– ±15-kV Air Gap Discharge• IEC 61000-4-4 EFT Protection– 80 A (5/50 ns)• IEC 61000-4-5 Surge Protection– 2.5 A (8/20 µs)• IO Capacitance 0.42 pF to 0.5 pF (Typical)• DC Breakdown Voltage 6.5 V (Minimum)• Ultra low Leakage Current 10 nA (Maximum)• Low ESD Clamping Voltage• Industrial Temperature Range: –40°C to +125°C• Easy Straight-Through Routing Packages2 Applications• HDMI 1.4b• HDMI 2.0• USB 3.0• MHL• LVDS Interfaces• DisplayPort• PCI-Express®• eSata Interfaces• V-by-One® HS3 DescriptionThe TPDxE05U06 is a family of unidirectionalTransient Voltage Suppressor (TVS) basedElectrostatic Discharge (ESD) protection diodes withultra-low capacitance. Each device can dissipate ESDstrikes above the maximum level specified by the IEC61000-4-2 international standard. The TPDxE05U06sultra-low loading capacitance makes it ideal forprotecting any high-speed signal pins.Typical applications for TPDxE05U06 includes highspeed signal lines in HDMI 1.4b, HDMI 2.0, USB 3.0,MHL, LVDS, DisplayPort, PCI-Express®, eSata, andV-by-One® HS.Device Information(1)PART NUMBER PACKAGE BODY SIZE (NOM)TPD1E05U06 X1SON (2) 0.60 mm × 1.00 mmTPD4E05U06 USON (10) 2.50 mm × 1.00 mmTPD6E05U06 USON (14) 3.50 mm × 1.35 mm(1) For all available packages, see the orderable addendum atthe end of the datasheet.Simplified Schematic TPD4E05U06 Functional Block Diagram2TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments IncorporatedTable of Contents1 Features.................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions......................... 46 Specifications......................................................... 66.1 Absolute Maximum Ratings ...................................... 66.2 ESD Ratings—JEDEC Specification......................... 66.3 ESD Ratings—IEC Specification .............................. 66.4 Recommended Operating Conditions....................... 66.5 Thermal Information.................................................. 66.6 Electrical Characteristics........................................... 76.7 Typical Characteristics .............................................. 87 Detailed Description ............................................ 107.1 Overview ................................................................. 107.2 Functional Block Diagram ....................................... 107.3 Feature Description................................................. 117.4 Device Functional Modes........................................ 118 Application and Implementation ........................ 128.1 Application Information............................................ 128.2 Typical Applications ................................................ 129 Power Supply Recommendations...................... 1610 Layout................................................................... 1610.1 Layout Guidelines ................................................. 1610.2 Layout Example .................................................... 1611 Device and Documentation Support ................. 1811.1 Documentation Support ........................................ 1811.2 Related Links ........................................................ 1811.3 Receiving Notification of Documentation Updates 1811.4 Community Resources.......................................... 1811.5 Trademarks ........................................................... 1811.6 Electrostatic Discharge Caution............................ 1811.7 Glossary ................................................................ 1912 Mechanical, Packaging, and OrderableInformation ........................................................... 194 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision K (November 2016) to Revision L Page• Updated DPY pinout image.................................................................................................................................................... 4• Updated title from TPD4E05U06 to TPD6E05U06 in Figure 13 .......................................................................................... 10Changes from Revision J (March 2016) to Revision K Page• Changed min value of VBR from "6 V" to "6.5 V" in the Electrical Characteristics table......................................................... 7Changes from Revision I (June 2015) to Revision J Page• Replaced all instances of X2SON with X1SON...................................................................................................................... 1• Update the Pin Functions table ............................................................................................................................................. 4• Added Power Supply Recommendations section................................................................................................................. 16Changes from Revision H (May 2015) to Revision I Page• Added Trademarks ................................................................................................................................................................ 1• Corrected TPD6E05U06 Pin 13 name ................................................................................................................................... 5• Corrected TLP definition ........................................................................................................................................................ 7Changes from Revision G (July 2014) to Revision H Page• Added Additional Application.................................................................................................................................................. 1• Updated with HDMI 2.0 Eye Diagrams................................................................................................................................. 133TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation FeedbackChanges from Revision F (November 2013) to Revision G Page• Added 61000-4-4 EFT compliance......................................................................................................................................... 1• Added Handling Ratings table................................................................................................................................................ 6• Added Thermal Information table. ......................................................................................................................................... 6• Added Detailed Description section. .................................................................................................................................... 10• Added Application and Implementation section. ................................................................................................................. 12• Added Layout section. ......................................................................................................................................................... 16Changes from Original (December 2012) to Revision A Page• Added TPS2EUSB30A part to document............................................................................................................................... 1Changes from Revision A (December 2012) to Revision B Page• Added Insertion Loss Graphic. ............................................................................................................................................... 9• Added Eye Diagrams............................................................................................................................................................ 13Changes from Revision B (January 2013) to Revision C Page• Changed IO Capacitance range............................................................................................................................................. 1• Changed test conditions and typ values for Vclamp ................................................................................................................. 7• Added typ RDYN values for DQA and RVZ packages ............................................................................................................. 7• Added CL values for DQA and RVZ packages....................................................................................................................... 7• Changed CURRENT vs VOLTAGE graphic........................................................................................................................... 8• Changed Insertion Loss graphic............................................................................................................................................. 9• Changed HDMI Eye Diagrams ............................................................................................................................................. 13Changes from Revision C (March 2013) to Revision D Page• Updated Title. ......................................................................................................................................................................... 1• Removed Ordering Information table. .................................................................................................................................... 4Changes from Revision D (August 2013) to Revision E Page• Updated document formatting. ............................................................................................................................................... 1• Added additional application................................................................................................................................................... 1NCNCNCNCGNDNCNCD1+D1–D2+D2–GNDD3+D3–1234567 891011121314D1+ 12345 678910D1–GNDD2+D2–NCNCGNDNCNC12I/OGND4TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated5 Pin Configuration and FunctionsDPY Package2-Pin X1SONTop ViewDQA Package10-Pin USONTop View(1) Place as close to the connector as possible.RVZ Package14-Pin USONTop ViewPin Functions TPD1E05U06 DPYPINTYPE DESCRIPTIONNAME NO.GND 2 Ground Ground; Connect to groundI/O 1 I/O ESD protected channel(1)(1) Place as close to the connector as possible.Pin Functions TPD4E05U06 DQAPINTYPE DESCRIPTIONNAME NO.D1+ 1 I/O ESD protected channel(1)D1– 2 I/O ESD protected channel(1)D2+ 4 I/O ESD protected channel(1)D2– 5 I/O ESD protected channel(1)5TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation FeedbackPin Functions TPD4E05U06 DQA (continued)PINTYPE DESCRIPTIONNAME NO.GND 3Ground Ground; Connect to groundGND 8NC 6— Not connected; Used for optional straight-through routing. Can be left floating or groundedNC 7NC 9NC 10(1) Place as close to the connector as possible.Pin Functions TPD6E05U06 RVZPINTYPE DESCRIPTIONNAME NO.D1+ 14 I/O ESD protected channel(1)D1– 13 I/O ESD protected channel(1)D2+ 12 I/O ESD protected channel(1)D2– 11 I/O ESD protected channel(1)D3+ 9 I/O ESD protected channel(1)D3– 8 I/O ESD protected channel(1)GND 5Ground Ground; Connect to groundGND 10NC 1— Not connected; Used for optional straight-through routing. Can be left floating or groundedNC 2NC 3NC 4NC 6NC 76TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Absolute maximum ratings apply over recommended junction temperature range.(3) Voltages are with respect to GND unless otherwise noted.(4) Measured at 25°C.6 Specifications6.1 Absolute Maximum Ratings(1)(2)(3)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITElectrical fasttransient IEC 61000-4-4 (5/50 ns) 80 APeak pulseIEC 61000-4-5 Current (tp – 8/20 µs)(4) 2.5 AIEC 61000-4-5 Power (tp – 8/20 µs)(4) 40 WTA Operating temperature –40 125 °CTstg Storage temperature –65 155 °C(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 250-V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.6.2 ESD Ratings—JEDEC SpecificationVALUE UNITV(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±15006.3 ESD Ratings—IEC SpecificationVALUE UNITV(ESD) Electrostatic dischargeIEC 61000-4-2 contact discharge ±12000VIEC 61000-4-2 air-gap discharge ±150006.4 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)MIN MAX UNITVIO Input pin voltage 0 5.5 VTA Operating free-air temperature –40 125 °C(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.6.5 Thermal InformationTHERMAL METRIC(1)TPD1E05U06 TPD4E05U06 TPD6E05U06DPY (X1SON) DQA (USON) RVZ (USON) UNIT2 PINS 10 PINS 14 PINSRθJA Junction-to-ambient thermal resistance 697.3 327 197.9 °C/WRθJC(top) Junction-to-case (top) thermal resistance 471 189.5 119.1 °C/WRθJB Junction-to-board thermal resistance 575.9 257.7 92.6 °C/WψJT Junction-to-top characterization parameter 175.7 60.9 22 °C/WψJB Junction-to-board characterization parameter 575.1 257 91.6 °C/W7TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback(1) Transmission Line Pulse (TLP) with 100 ns width, 200 ps rise time.(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.(3) Capacitance data is taken at 25°C.6.6 Electrical Characteristicsover operating free-air temperature range (unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITVRWM Reverse stand-off voltage IIO < 10 µA 5.5 VVBR Break-down voltage IIO = 1 mA 6.5 8.5 VVclamp Clamp voltageI = 1 A, TLP, I/O to ground(1) 10VI = 5 A, TLP, I/O to ground(1) 14I = 1 A, TLP, ground to I/O(1) 3I = 5 A, TLP, ground to I/O(1) 7ILEAK Leakage current VIO = 2.5 V 0.01 10 nARDYNDPY package dynamicresistanceI/O to GND(2) 0.8ΩGND to I/O(2) 0.8DQA package dynamicresistanceI/O to GND(2) 0.8ΩGND to I/O(2) 0.8RVZ package dynamicresistanceI/O to GND(2) 0.8ΩGND to I/O(2) 0.8CapacitanceCL Line capacitance(3) VIO = 2.5 V, f = 1 MHz,I/O to GNDTPD1E05U06 DPYpackage 0.42pF TPD4E05U06 DQApackage 0.5TPD6E05U06 RVZpackage 0.47ΔCIO-TOGNDVariation of channel inputcapacitanceGND Pin = 0 V, F = 1 GHz, VBIAS = 2.5 V,channel_x pin to GND – channel_y pin to GND 0.05 0.07 pFCCROSSChannel to channel inputcapacitanceGND Pin = 0 V, F = 1 GHz, VBIAS = 2.5 V, betweenchannel pins 0.01 0.06 pF050100150200250300±40 ±20 0 20 40 60 80 100 120Current (pA)Temperature (ÉC) C004±10010203040506070800 25 50 75 100 125 150 175 200Voltage (V)Time (ns) C005±5051015202530350 5 10 15 20 25 30 35 40Current (A)Voltage (V) C00305101520250 5 10 15 20 25Current (A)Voltage (V) C008±1.0±0.8±0.6±0.4±0.20.00.20.40.60.81.0±2 ±1 0 1 2 3 4 5 6 7 8 9 10Current (mA)Voltage (V) C001051015202530354045500.00.51.01.52.02.53.03.5±5 0 5 10 15 20 25 30 35 40 45 50Current (A)Power (W)Time (s)CurrentPowerC0028TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated6.7 Typical CharacteristicsFigure 1. DC Voltage Sweep I-V Curve Figure 2. Surge Curve (tp = 8/20 μs), Pin IO to GNDFigure 3. Positive TLP Plot IO to GND Figure 4. Negative TLP Plot IO to GNDFigure 5. Leakage vs Temperature Figure 6. 8-kV IEC Waveform±6±5±4±3±2±10100k 1M 10M 100M 1000M 10000MInsertion Loss (dB)Frequency (Hz) C0091G 10G±6±5±4±3±2±10100k 1M 10M 100M 1000M 10000MInsertion Loss (dB)Frequency (Hz) C0101G 10G±90±80±70±60±50±40±30±20±100100 25 50 75 100 125 150 175 200Voltage (V)Time (ns) C006±12±11±10±9±8±7±6±5±4±3±2±10100k 1M 10M 100M 1000M 10000MInsertion Loss (dB)Frequency (Hz) C0071G 10G9TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation FeedbackTypical Characteristics (continued)Figure 7. –8-kV IEC Waveform Figure 8. TPD1E05U06 Insertion LossFigure 9. TPD4E05U06 Insertion Loss Figure 10. TPD6E05U06 Insertion LossD1+ D1- D2+ D2-GNDD3+ D3- D1+ D1- D2+ D2-GNDI/OGND10TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated7 Detailed Description7.1 OverviewThe TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) based Electrostatic Discharge(ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximumlevel specified by the IEC 61000-4-2 international standard. The TPDxE05U06s ultra-low loading capacitancemakes it ideal for protecting any high-speed signal pins.7.2 Functional Block DiagramFigure 11. TPD1E05U06 Block DiagramFigure 12. TPD4E05U06 Block DiagramFigure 13. TPD6E05U06 Block Diagram11TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback7.3 Feature DescriptionThe TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) Electrostatic Discharge (ESD)protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximum levelspecified by the IEC 61000-4-2 international standard. The TPDxE05U06s ultra-low loading capacitance makes itideal for protecting any high-speed signal pins.7.3.1 ±15-kV IEC61000-4-2 Level 4 ESD ProtectionThe I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air. An ESD-surge clamp diverts thecurrent to ground.7.3.2 IEC61000-4-4 EFT ProtectionThe I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ωimpedance). An ESD-surge clamp diverts the current to ground. This has been validated on the TPD4E05U06only.7.3.3 IEC61000-4-5 Surge ProtectionThe I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD-surge clamp divertsthis current to ground.7.3.4 I/O CapacitanceThe capacitance between each I/O pin to ground is 0.42 pF (TPD1E05U06), 0.5 pF (TPD4E05U06) or 0.47 pF(TPD6E05U06). These devices support data rates up to 6 Gbps.7.3.5 DC Breakdown VoltageThe DC breakdown voltage of each I/O pin is a minimum of 6 V. This ensures that sensitive equipment isprotected from surges above the reverse standoff voltage of 5 V.7.3.6 Ultra-Low Leakage CurrentThe I/O pins feature an ultra-low leakage current of 10 nA (max) with a bias of 2.5 V.7.3.7 Low ESD Clamping VoltageThe I/O pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A).7.3.8 Industrial Temperature RangeThis device features an industrial operating range of –40°C to +125°C.7.3.9 Easy Flow-Through RoutingThe layout of this device makes it simple and easy to add protection to an existing layout. The packages offersflow-through routing, requiring minimal modification to an existing layout.7.4 Device Functional ModesThe TPDxE05U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lowerdiodes Vf(–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internaldiode network. When the voltages on the protected line fall below the trigger levels of TPDxE05U06 (usuallywithin 10s of nano-seconds) the device reverts to passive.HOT PLUG 1UTILITY 2TMDS D2+ 3TMDS_GND 4TMDS D2- 5TMDS D1+ 6TMDS_GND 7TMDS D1- 8TMDS D0+ 9TMDS_GND 10TMDS D0- 11TMDS CLK+ 12TMDS_GND 13TMDS CLK- 14CEC 15DDC/CEC GND 16SCL 17SDA 18P 5V0 19GND 20HDMI Connector12345 67891012345 678910CEC_CONSCL_CONSDA_CONEN5V_CONHPD_CONUTI_CON GNDHPD_SYS5V_SYSVCCASDA_SYSSCL_SYSCEC_SYSUTI_COND2+D2-D1+D1-D0+D0-CLK+CLK0.1 µF 0.1 µF UTI_COND2+D2-D1+D1-D0+D0-CLK+CLK5V SourceHDMI ControllerTPD4E05U06DQATPD4E05U06DQATPD5S116YFF12TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated8 Application and ImplementationNOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.8.1 Application InformationThe TPDxE05U06 is a diode type TVS which is typically used to provide a path to ground for dissipating ESDevents on hi-speed signal lines between a human interface connector and a system. As the current from ESDpasses through the TVS, only a small voltage drop is present across the diode. This is the voltage presented tothe protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protectedIC.8.2 Typical Applications8.2.1 HDMI 2.0 ApplicationFigure 14. HDMI 2.0 Schematic13TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation FeedbackTypical Applications (continued)8.2.1.1 Design RequirementsFor this design example, the two TPD4E05U06 devices, and a TPD5S116 are being used in an HDMI 2.0application. This provides a complete port protection scheme.Given the HDMI 2.0 application, the parameters listed in Table 1 are known.Table 1. Design ParametersDESIGN PARAMETER VALUESignal range on pins 1, 2, 4, or 5 0 V to 5 VOperating frequency 3 GHz8.2.1.2 Detailed Design Procedure8.2.1.2.1 Signal Range on Pin 1, 2, 4, or 5The TPD4E05U06 has 4 identical protection channels for signal lines. The symmetry of the device providesflexibility when selecting which of the 4 I/O channels is going to protect which signal lines. Any I/O supports asignal range of 0 to 5.5 V.8.2.1.3 Application CurvesFigure 15. 3.4-Gbps HDMI 1.4 TP1 Eye DiagramUnpopulated EVMFigure 16. 3.4-Gbps HDMI 1.4 TP1 Eye DiagramTPD1E05U06Figure 17. 3.4-Gbps HDMI 1.4 TP1 Eye DiagramTPD4E05U06Figure 18. 3.4-Gbps HDMI 1.4 TP1 Eye DiagramTPD6E05U061212ConnectorHDMI 2.0 ControllerTPD1E05U06TPD1E05U06D0-D1+D1-D2+D2-CLK+CLKD0+GND GND2TPD1E05U062GNDTPD1E05U062GNDTPD1E05U06 GND1112TPD1E05U062GNDTPD1E05U062GNDTPD1E05U06 GND11114TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments IncorporatedFigure 19. 6-Gbps HDMI 2.0 (TP1) Eye DiagramUnpopulated EVMFigure 20. 6-Gbps HDMI 2.0 (TP1) Eye DiagramTPD1E05U06Figure 21. 6-Gbps HDMI 2.0 (TP1) Eye DiagramTPD4E05U06Figure 22. 6-Gbps HDMI 2.0 (TP1) Eye DiagramTPD6E05U068.2.2 HDMI 2.0 ApplicationFigure 23. HDMI 2.0 Schematic15TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback8.2.2.1 Design RequirementsFor this design example, the TPD1E05U06 and the TPD5S116 are used to protect the data pairs and controllines of the HDMI 2.0 connection. This provides full HDMI 2.0 port protection.Given the HDMI 2.0 application, the following parameters in Table 2 are known.Table 2. Design ParametersDESIGN PARAMETER VALUESignal range on data lines 0 V to 5 VOperating frequency 3 GHz8.2.2.2 Detailed Design Procedure8.2.2.2.1 Signal RangeThe TPD1E05U06 has 1 protection channel for signal lines, supporting a signal range of 0 V to 5.5 V.8.2.2.2.2 Operating FrequencyThe TPD1E05U06 has 0.42 pF of capacitance, which supports HDMI 2.0 data rates.8.2.2.3 Application CurvesRefer to the Application Curves section.VIA to GND Plane D2+ D2- D1+D1-D0+D0-Clk+ClkD1- D1+ D0- D0+ NCNCNCNC GND GND NCNCNCNC GND NCNCNCNCD1-D1+GNDD0-D0+16TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated9 Power Supply RecommendationsThis device is a passive ESD protection device and there is no need to power it. Care must be taken to makesure that the maximum voltage specifications for each line are not violated.10 Layout10.1 Layout Guidelines• The optimum placement is as close to the connector as possible.– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,resulting in early system failures.– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected tracesaway from the protected traces which are between the TVS and the connector.• Route the protected traces as straight as possible.• Eliminate any sharp corners on the protected traces between the TVS and the connector by using roundedcorners with the largest radii possible.– Electric fields tend to build up on corners, increasing EMI coupling.10.2 Layout Example10.2.1 TPD4E05U06 Layout ExampleThis application is typical of an HDMI 1.4 layout.Figure 24. TPD4E05U06 LayoutD2+D2-D1+D1-D0+D0-Clk+ClkVIA to GND Plane I/O GND I/O GND I/O GND I/O GND I/O GND I/O GND I/O GNDI/OGND17TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation FeedbackLayout Example (continued)10.2.2 TPD1E05U06 Layout ExampleThis application is typical of an HDMI 2.0 layout.Figure 25. TPD1E05U06 Layout18TPD1E05U06, TPD4E05U06, TPD6E05U06SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017 www.ti.comProduct Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated11 Device and Documentation Support11.1 Documentation Support11.1.1 Related DocumentationFor related documentation see the following:• Reading and Understanding an ESD Protection Datasheet• ESD Layout Guide• TPD6E05U06RVZ EVM User's Guide• Picking ESD Diodes for Ultra High-Speed Data Lines• ESD PROTECTION DIODES EVM• TPD1E05U06DPY EVM User's Guide• TPD4E05U06DQA EVM User's Guide11.2 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.Table 3. Related LinksPARTS PRODUCT FOLDER SAMPLE & BUY TECHNICALDOCUMENTSTOOLS &SOFTWARESUPPORT &COMMUNITYTPD1E05U06 Click here Click here Click here Click here Click hereTPD4E05U06 Click here Click here Click here Click here Click hereTPD6E05U06 Click here Click here Click here Click here Click here11.3 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates—including silicon errata—go to the product folder for yourdevice on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weeklydigest of product information that has changed (if any). For change details, check the revision history of anyrevised document.11.4 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.11.5 TrademarksE2E is a trademark of Texas Instruments.PCI-Express is a registered trademark of PCI-SIG .V-by-One is a registered trademark of Thine Electronics, Inc.All other trademarks are the property of their respective owners.11.6 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.19TPD1E05U06, TPD4E05U06, TPD6E05U06www.ti.com SLVSBO7L –DECEMBER 2012–REVISED JANUARY 2017Product Folder Links: TPD1E05U06 TPD4E05U06 TPD6E05U06Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback11.7 GlossarySLYZ022 — TI Glossary.This glossary lists and explains terms, acronyms, and definitions.12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.PACKAGE OPTION ADDENDUMwww.ti.com 10-Dec-2020Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEco Plan(2)Lead finish/Ball material(6)MSL Peak Temp(3)Op Temp (°C) Device Marking(4/5)SamplesTPD1E05U06DPYR ACTIVE X1SON DPY 2 10000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (BK, C1, C6)C2TPD1E05U06DPYT ACTIVE X1SON DPY 2 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (BK, C1, C6)C2TPD4E05U06DQAR ACTIVE USON DQA 10 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (BLG, BRG)BRYTPD6E05U06RVZR ACTIVE USON RVZ 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (BV, BVY)(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as &quotb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andPACKAGE OPTION ADDENDUMwww.ti.com 10-Dec-2020Addendum-Page 2continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF TPD1E05U06, TPD4E05U06 :•Automotive: TPD1E05U06-Q1, TPD4E05U06-Q1NOTE: Qualified Version Definitions:•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defectsTAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantTPD1E05U06DPYR X1SON DPY 2 10000 180.0 9.5 0.66 1.15 0.66 2.0 8.0 Q1TPD1E05U06DPYR X1SON DPY 2 10000 180.0 8.4 0.07 1.1 0.47 2.0 8.0 Q1TPD1E05U06DPYT X1SON DPY 2 250 180.0 8.4 0.07 1.1 0.47 2.0 8.0 Q1TPD1E05U06DPYT X1SON DPY 2 250 180.0 9.5 0.66 1.15 0.66 2.0 8.0 Q1TPD4E05U06DQAR USON DQA 10 3000 180.0 9.5 1.23 2.7 0.7 4.0 8.0 Q1TPD4E05U06DQAR USON DQA 10 3000 180.0 9.5 1.18 2.68 0.72 4.0 8.0 Q1TPD4E05U06DQAR USON DQA 10 3000 180.0 8.4 1.23 2.7 0.6 4.0 8.0 Q1TPD6E05U06RVZR USON RVZ 14 3000 180.0 13.2 1.65 3.8 0.7 4.0 12.0 Q1TPD6E05U06RVZR USON RVZ 14 3000 178.0 13.5 1.6 3.75 0.7 4.0 12.0 Q1PACKAGE MATERIALS INFORMATIONwww.ti.com 24-Jul-2020Pack Materials-Page 1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)TPD1E05U06DPYR X1SON DPY 2 10000 184.0 184.0 19.0TPD1E05U06DPYR X1SON DPY 2 10000 203.2 196.8 33.3TPD1E05U06DPYT X1SON DPY 2 250 203.2 196.8 33.3TPD1E05U06DPYT X1SON DPY 2 250 184.0 184.0 19.0TPD4E05U06DQAR USON DQA 10 3000 184.0 184.0 19.0TPD4E05U06DQAR USON DQA 10 3000 189.0 185.0 36.0TPD4E05U06DQAR USON DQA 10 3000 203.2 196.8 33.3TPD6E05U06RVZR USON RVZ 14 3000 184.0 184.0 19.0TPD6E05U06RVZR USON RVZ 14 3000 189.0 185.0 36.0PACKAGE MATERIALS INFORMATIONwww.ti.com 24-Jul-2020Pack Materials-Page 2www.ti.comPACKAGE OUTLINEC8X 0.250.1510X 0.430.302X24X 0.50.55 MAX0.050.002X 0.450.35B 1.10.9A2.62.4(0.13) TYP(R0.125)DQA0010A USON - 0.55 mm max heightPLASTIC SMALL OUTLINE - NO LEAD4220328/A 12/2015PIN 1 INDEX AREASEATING PLANE0.08 C15 610(OPTIONAL)PIN 1 ID0.1 C A B0.05 C0.1 C A B0.05NOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancingper ASME Y14.5M.2. This drawing is subject to change without notice.SCALE 6.000www.ti.comEXAMPLE BOARD LAYOUT0.07 MINALL AROUND0.07 MAXALL AROUND4X (0.5)(0.835)8X (0.2)10X (0.565)(R0.05) TYP2X (0.4)DQA0010A USON - 0.55 mm max heightPLASTIC SMALL OUTLINE - NO LEAD4220328/A 12/2015SYMM15610SYMMLAND PATTERN EXAMPLESCALE:30XNOTES: (continued)3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).SOLDER MASKSOLDER MASK OPENINGMETAL UNDERSOLDER MASKDEFINEDSOLDER MASK METALOPENINGSOLDER MASK DETAILSNON SOLDER MASKDEFINED(PREFERRED)www.ti.comEXAMPLE STENCIL DESIGN8X (0.2)10X (0.565)4X (0.5)2X (0.36)(0.835)(R0.05) TYPDQA0010A USON - 0.55 mm max heightPLASTIC SMALL OUTLINE - NO LEAD4220328/A 12/2015NOTES: (continued)4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCILEXPOSED PADS 3 & 8:90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:40XSYMM15 610SYMMMETALTYP3 8www.ti.comPACKAGE OUTLINEC0.450.300.050.000.650.1 C A B2X 0.550.452X 0.30.2A 1.10.9 B0.70.54224561/B 03/2021DPY0002A X1SON - 0.45 mm max heightPLASTIC SMALL OUTLINE - NO LEADPIN 1 INDEX AREASEATING PLANE0.08 C1 20.05 C A BSYMMSYMMNOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancingper ASME Y14.5M2. This drawing is subject to change without notice.SCALE 11.000www.ti.comEXAMPLE BOARD LAYOUT0.07 MINALL AROUND 0.07 MAXALL AROUND(R0.05) TYP(0.7)2X (0.5)2X (0.3)4224561/B 03/2021DPY0002A X1SON - 0.45 mm max heightPLASTIC SMALL OUTLINE - NO LEADSYMM1 2SYMMLAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:60XNOTES: (continued)3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.It is recommended that vias under paste be filled, plugged or tented.SOLDER MASK DETAILSMETAL EDGESOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINEDMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALSOLDER MASKDEFINED(PREFERRED)www.ti.comEXAMPLE STENCIL DESIGN(R0.05) TYP(0.7)2X (0.5)2X (0.3) (0)4224561/B 03/2021DPY0002A X1SON - 0.45 mm max heightPLASTIC SMALL OUTLINE - NO LEADNOTES: (continued)5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCILSCALE:60XSYMM1 2SYMMPCB PAD METALUNDER SOLDER PASTEIMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. 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