二维晶体管CCP缩放至60nm

Au/Ti/Ni 和 Ni/Au 接触电极的比较

a, Device structure of the scaled MoS2 FETs. For a back-gated transistor, CPP is determined by the sum of Lch and Lc, where Lg could be equal to Lch. To realize the all-out scaling of CPP, Lch and Lc need to be simultaneously reduced. S, source; D, drain; BG, back-gate. b, Magnified view of the source contact, revealing the injection of electrons through the bottom edge of the contact and corresponding to LT. Below the diagram, schematic showing the resistor network model of contact resistance at the metal–semiconductor interface, includes the specific contact resistivity (ρc, units: Ω cm2) and sheet resistance (units: Ω per square) underneath the contact (Rsh-c) and in the channel (Rsh-ch). The normalized potential V(x) under the contact versus position (x) is depicted as a function of ρc. Here LT represents the length where the potential decreases to ‘1/е’ of its original value (~36.8%) and е denotes Euler’s number. Above the diagram, SEM images of Au and Ni electrodes are presented. Scale bar, 100 nm. Au electrodes show a granular structure due to clustering, while Ni electrodes exhibit a more homogeneous and small-size structure. Schematic of composite metals Au/Ti/Ni as contact electrodes, aims to not only enhance shape-preserving effect for achieving the extreme scaling of Lc, but also maintain a low Rc. c, Transfer curves of MoS2 FETs using a TLM structure with Lch varying from 0.2 μm to 1.0 μm, in which Wch is fixed at 500 nm and Lc is fixed at 1.0 μm. The inset is an SEM image of the TLM structure. Scale bar, 3 μm. d, Rtot (normalized by width) versus Lch at various carrier densities from the TLM method. Rc can be extracted by linear fitting to the data points and subsequent extrapolation of half the y-axis intercept, while LT is obtained from half the x-axis intercept. e, A summary of the Rc and LT estimated from the TLM structure as a function of n2D, with two different types of contact electrodes, Au/Ti/Ni and Ni/Au, respectively.CPP 全面缩放至 60 nm

a, SEM images of a representative MoS2 FET with CPP of ~60 nm. CPP is close to the minimum reported record, with both Lc and Lch reduced to ~30 nm. Scale bars, 100 nm and 50 nm, respectively (left). Cross-sectional TEM and the corresponding EDS elemental mapping of fabricated MoS2 FET. Scale bar, 10 nm (right). b, Ids–Vgs curves of the all-out scaled MoS2 FET (CPP = 60 nm) with Au/Ti/Ni contacts. c, Ids–Vds curves for the all-out scaled devices using Au/Ti/Ni and Ni/Au contact electrodes, respectively. d, Ion values of the scaled MoS2 FETs for Lc scaling from 500 nm to 30 nm, together with Lch scaled to 30 nm. e, Benchmark of CPP versus Ion of monolayer MoS2 FETs with different contact configurations at a drain-source voltage of 1.0 V. f, Comparison of Ion versus Ioff at various Vds values (increasing from left to right) for the scaled MoS2 FETs in this work with commercial Si FETs from 32 nm to 10 nm technology node, as well as other representative scaled CNT and MoS2 transistors. It is noted that Ion represents the maximum on-state current and Ioff denotes the minimum off-state current.缩放 2D FET 阵列 （Lch= Lc= 30 nm）

a, Three-dimensional schematic of the all-out scaled MoS2 FET arrays. b, Magnified view of a group of all-out scaled MoS2 FETs. Scale bar, 100 μm. c, A group consists of six MoS2 FETs. Scale bar, 20 μm. d, Ids–Vgs curves for the arrays with a fixed drain-source bias of 1.0 V, exhibiting a high yield of 82.5%. The blue curve describes a typical transfer curve in the scaled MoS2 FET arrays. e, Ion distribution obtained from the transfer curves. The x and y values represent device indices in two directions. The grey gridlines clearly illustrate that the array consists of 20 groups of 2 × 3 sub-arrays, corresponding to a total of 120 devices. Each group contains six MoS2 FETs, consistent with the optical microscope images of all-out scaled 2D FET arrays. f, SEM images of 20 representative devices, demonstrating a uniform scaled device configuration. Scale bar, 100 nm. g–i, The statistical histograms and Gaussian fits of on/off ratio (g), threshold voltage (h) and transconductance (i).缩放逻辑门电路 （Lch= Lc= 30 nm）

a, Equivalent circuit diagrams of logic gate circuits, which are constructed using all-out scaled MoS2 FETs as building blocks, including inverters, NAND, NOR and AND gates. The inverter is fabricated by a pair of identical MoS2 FETs serving as driver and load transistors, respectively. GND, ground (zero potential). b, Voltage transfer curve of the scaled MoS2 inverter at Vdd = 1.0 V, the corresponding voltage gain is ∼14 V/V. c,d, Output waveforms (c) and the corresponding Vout results (d) for scaled NAND, NOR and AND gates at Vdd = 1.0 V as functions of VA and VB, respectively. Vin are composed of ±1.0 V pulses for VA and VB, with a delay of 20 ms. Vout of 1.0 V designates the logic state ‘1’, while 0 V represents the logic state ‘0’.结论

使用复合金属 Au/Ti/Ni 接触电极，单层 MoS2 FET 可以缩放到大约 60 nm 的 CPP（Lc 和 Lch 都低至 ~30 nm，LT < 30 nm）。这种策略增强了保形效果，以实现 Lc 的极端缩放，同时保持低 Rc。具有 60 nm CPP 的全面缩放 MoS2 FET 表现出有竞争力的性能，包括超过 8个 开/关比、电流密度~300 μA μm-1 （CPP = 80 nm 时为 ~700 μA μm-1）和 ~1 pA μm-1 的 Ioff，满足 IRDS2034 的目标。展示 60 nm CPP FET 的大型阵列，在关键性能指标方面具有高均一性，这突出了集成到高级逻辑电路中的潜力。该结果为 2D 晶体管在先进架构（如三维集成电路或小芯片）中的未来应用提供了基础。然而，全面扩展的 2D 晶体管的大规模集成在晶圆级材料合成和转移方面仍面临挑战，这需要新兴技术才能完全解决。

工艺制造全尺寸 MoS2FET 和阵列

全面缩放的 MoS2 FET 和阵列的制造过程需要在多层结构之间进行高精度的图形对齐嵌套曝光。首先，在 Si/SiNx 衬底上用 Cr/Au （5/45 nm） 制造用于对准嵌套的全局标记和芯片标记。其次，分别使用电子束光刻 （EBL） 和电子束蒸发 （EBE） 对 Ti/Au/Ti （3/10/1 nm） 的局部背栅电极进行图案化和沉积。然后，通过等离子体氧化处理 20 s 制备电极表面，将顶部 Ti 层变成 TiO2 缓冲层。此外，在 180 °C 下通过原子层沉积将 7 nm 厚的 HfO2 沉积为栅极电介质。 接下来，使用聚苯乙烯辅助转移工艺将单层 MoS2 薄膜转移到介电层上，然后在 N2 气氛下进行 200 °C 2.5 h 的退火工艺。通道区域由 EBL 定义并由 O 2 干蚀 30 秒。最后，采用双步曝光法制造源极-漏极触点和测试焊盘。源极-漏极触点由束流为 500 pA 的 100 kV EBL 系统定义，然后通过我们的优化工艺沉积复合金属 Au/Ti/Ni （3/2/15 nm）。互连线和焊盘通过激光直写进行图案化，并使用 EBE 沉积 Cr/Au （5/35 nm）。Lch = Lc = 30 nm 的全尺寸逻辑门电路是使用相同的工艺制造的。