DS_4GB_4G_D_DDR4_Samsung_Spec_Rev141

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DS_4GB_4G_D_DDR4_Samsung_Spec_Rev141

• JEDEC standard 1.2V (1.14V~1.26V)
• V
DDQ = 1.2V (1.14V~1.26V)
• 800 MHz f
CK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin,
1067MHz f
CK for 2133Mb/sec/pin, 1200MHz fCK for2400Mb/sec/pin
• 16 Banks (4 Bank Groups)
• Programmable CAS Latency(posted CAS):
10,11,12,13,14,15,16,17,18
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600) ,
10,12 (DDR4-1866) ,11,14 (DDR4-2133) and 12,16 (DDR4-2400)
• 8-bit pre-fetch
• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read
or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at
85C < T
CASE < 95 C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
• CRC(Cyclic Redundancy Check) for Read/Write data security
• Command address parity check
• DBI(Data Bus Inversion)
• Gear down mode
• POD (Pseudo Open Drain) interface for data input/output
• Internal VREF for data inputs
• External VPP for DRAM Activating Power
• PPR is supported




DS_4GB_4G_D_DDR4_Samsung_Spec_Rev141.pdf (1.93 MB, 下载次数: 1)

2016-6-16 08:57 上传

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bidezhi7777

谢谢分享，好资料也叫好！！！