• Xilinx Zynq 7010/7020 CLG400 AP SOC
o Primary configuration = QSPI Flash
o Auxiliary configuration options
JTAG (through PL via Xilinx PC4 Header)
microSD Card
• Memory
o 1 GB DDR3 (x32)
o 128 Mb QSPI Flash
o 4 GB microSD Card (Evaluation Kit only, AES-Z7MB-7Z010-G)
• Interfaces
o Xilinx PC4 Header for programming
Accesses Programmable Logic (PL) JTAG
Processing System (PS) JTAG pins connected through Digilent Pmod™
compatible interface
o 10/100/1000 Ethernet
o USB Host 2.0
o microSD Card
o USB 2.0 Full-Speed USB-UART bridge
o One Digilent Pmod compatible interface, connected to PS MIO
o Two 100-pin MicroHeaders
o Reset Button
o 1 User Push Button
o 1 User LEDs
o DONE LED
• On-board Oscillator
o 33.333 MHz
• Power
o High-efficiency regulators for Vccint, Vccpint, Vccbram, Vccaux, Vccpaux, Vccpll,
Vcco_0, Vcco_ddr, Vcco_mio
o Three potential powering methods
USB Bus Power from USB-UART interface
Optional barrel jack and AC/DC supply
Optional carrier card