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我在原理图中，只画了一个电阻，添加好了封装（封装是系统自带的），生成网表时，报下面错误：
Loading... c:\testfiles\sch\allegro/pstxprt.dat
#77 ERROR(SPCODD-77): Could not open file c:\testfiles\sch\allegro/pstxprt.dat.
You might be trying to reuse a design with an inaccessible state file. To reuse a design, ensure that the design being reused is treated as a subdesign and the subdesign state file is accessible and readable. To create the subdesign state file, use the GEN_SUBDESIGN directive.
ERROR(SPCODD-382): Error at line 1 in file c:\testfiles\sch\allegro/pstxprt.dat. Error loading the parts list file
#1 Error [ALG0036] Unable to read logical netlist data.
求解决办法？？？？？？？？？？[sub][/sub][sup][/sup][strike][/strike] |
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