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百度网盘
DATE: 10-25-2013 HOTFIX VERSION: 018
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL
1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.
1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.
1189100 SCM OTHER Replace part in SCM using ADW as library fails
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks
1194597 FSP OTHER Pin definition problem
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
1195309 GRE CORE GRE crashing during Plan Spatial.
1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
1198521 CONCEPT_HDL OTHER Cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1
1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped
1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist
1199323 GRE IFP_INTERACTIVE Crash when importing logic
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours
1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer |
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